AR# 75764

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Versal ACAP Programmable Network on Chip and Integrated Memory Controller - IP Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the Versal ACAP Programmable Network on Chip and Integrated Memory Controller IP Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History


Memory IP Page:

https://www.xilinx.com/products/technology/memory.html#externalMemory

 

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Please seek technical support via the Memory Interfaces and NoC Board. The Xilinx Forums are a great resource for technical support.

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Solution

General Information

Version History

Versal ACAP Programmable Network on Chip and Integrated Memory Controller Version

Vivado Tools Version
v1.02020.2

NoC Known and Resolved Issues

Answer RecordTitleVersion Found
Version Resolved
(Xilinx Answer 75711)Versal GTYE5_QUAD and NoC designs in Vivado 2020.2 using Aldec-Riviera do not produce a successful simulation2020.22020.2
(Xilinx Answer 75783)Versal ACAP Programmable Network on Chip: AXI4-Stream 1:M and N:M configurations are not supported2020.2Not resolved
(Xilinx Answer 75792)Versal ACAP Programmable Network on Chip:AXI4-Stream across INI is not supported2020.2Not resolved
(Xilinx Answer 75873)Versal ACAP Programmable Network on Chip: Isochronous Traffic is not fully supported2020.2Not resolved
(Xilinx Answer 75874)Versal ACAP Programmable Network on Chip: System C and RTL models frequency limitation2020.22021.1
(Xilinx Answer 75875)Versal ACAP Programmable Network on Chip: Parity from endpoints is not fully supported2020.22021.1
(Xilinx Answer 75876)Versal ACAP Programmable Network on Chip: Non-power-of-2 address ranges are not supported2020.22021.1
(Xilinx Answer 75983)Versal ACAP Programmable Network on Chip: Simulation supported for limited project structures2020.22021.1
(Xilinx Answer 76041)Versal ACAP Programmable Network on Chip: Limited support for WRAP bursts2020.2NA
(Xilinx Answer 76085)Versal ACAP Programmable Network on Chip: Empty port list in *_sim_wrapper.v2020.22020.3

DDRMC Known and Resolved Issues

Answer RecordTitleVersion Found
Version Resolved
(Xilinx Answer 76040)Versal ACAP DDRMC - DDR4 Intermittent CAL_DONE Failure Asserted when ECC and CA Parity are Enabled for Unbuffered Memory Topologies2020.22020.3
(Xilinx Answer 76058)Versal ACAP DDRMC - DDR4 RDIMM Single Slot Single Rank Optimum Pinout has CK_T and CK_P Sites Swapped in the Nibble2020.2Never Fix
(Xilinx Answer 76059)Versal ACAP DDRMC - DDR4 and LPDDR4/x PCB Simulation Support Article2020.2NA
(Xilinx Answer 76060)Versal ACAP DDRMC - Updated LPDDR4/x IBIS Model for LVSTL06_12 I/O Standard2020.22020.3
(Xilinx Answer 76061)Versal ACAP DDRMC - DDR4/LPDDR4x IBIS Model Export Does not Follow Model Selector Format2020.2Not Resolved
(Xilinx Answer 76063)Versal ACAP DDRMC - Critical Warning - Failed to Copy DDRMC Design Sources During Project Archiving and Design Runs Out of Date when Opening Archive2020.2Not Resolved
(Xilinx Answer 76064)Versal ACAP DDRMC - LPDDR4/x Per Bank Refresh Not Supported with Dual Rank Memory Topologies2020.2Never Fix
(Xilinx Answer 76065)Versal ACAP DDRMC - Vivado Hardware Manager DDRMC Write Calibration Margins Not Fully Captured in Left Aligned Chart Mode2020.2Never Fix
(Xilinx Answer 76067)Versal ACAP DDRMC - Vivado Hardware Manager DDRMC Calibration Status Does not Show Any Calibration Margins when Calibration is Successful2020.2Not Resolved
(Xilinx Answer 76108)Versal ACAP DDRMC - LPDDR4x Power Estimates Not Captured in XPE2020.2Not Resolved
(Xilinx Answer 76109)Versal ACAP DDRMC - Multi-Rank DDR4 Designs Not Driving CK or CKE for the Second Rank in Simulation2020.2Not Resolved
(Xilinx Answer 76111)Versal ACAP DDRMC - DDR4 with Mixed Write/Read Patterns and High Page Miss Counts Result in Starved Read Channels and High Max Read Latency2020.22021.1
(Xilinx Answer 76117)Versal ACAP DDRMC - DDR4 RESET_N Voltage Level Mismatch Analysis2020.2NA
(Xilinx Answer 76254)Design Advisory for Versal DDRMC - Pinouts Generated with User Specified DQS Byte Swaps for LPDDR4 and x8 or x16 DDR4 Component Interfaces May Contain Errors Requiring PCB Changes2020.22020.3
(Xilinx Answer 76283)Versal ACAP DDRMC - DDRMC XPLL Expectations and User LOC Constraint Interactions2020.22021.1

Version History
  • 11/18/2020 - Initial Release
  • 02/10/2021 - Updated DDRMC Known and Resolved Issues table
  • 04/28/2021 - Added DAAR#76254; Added AR#76283

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
75792 Versal ACAP Programmable Network on Chip: AXI4-Stream across INI is not supported N/A N/A
75783 Versal ACAP Programmable Network on Chip: AXI4-Stream 1:M and N:M configurations are not supported N/A N/A
75711 Versal: GTYE5_QUAD and NoC design have simulation issue with Aldec Riviera-PRO N/A N/A
75873 Versal ACAP Programmable Network on Chip: Isochronous Traffic is not fully supported N/A N/A
75874 Versal ACAP Programmable Network on Chip: System C and RTL models frequency limitation N/A N/A
75875 Versal ACAP Programmable Network on Chip: Parity from endpoints is not fully supported N/A N/A
75876 Versal ACAP Programmable Network on Chip: Non-power-of-2 address ranges are not supported N/A N/A
75983 Versal ACAP Programmable Network on Chip: Simulation supported for limited project structures N/A N/A
76041 Versal ACAP Programmable Network on Chip: Limited support for WRAP bursts N/A N/A
76085 Versal ACAP Programmable Network on Chip: Empty port list in *_sim_wrapper.v N/A N/A
76058 Versal ACAP DDRMC - DDR4 RDIMM Single Slot Single Rank Optimum Pinout has CK_T and CK_P Sites Swapped in the Nibble N/A N/A
76060 Versal ACAP DDRMC - Updated LPDDR4/x IBIS Model for LVSTL06_12 I/O Standard N/A N/A
76061 Versal ACAP DDRMC - DDR4/LPDDR4x IBIS Model Export Does not Follow Model Selector Format N/A N/A
76063 Versal ACAP DDRMC - Critical Warning Failed to Copy DDRMC Design Sources During Project Archiving and Design Runs Out of Date when Opening Archive N/A N/A
76064 Versal ACAP DDRMC - LPDDR4/x Per Bank Refresh Not Supported with Dual Rank Memory Topologies N/A N/A
76065 Versal ACAP DDRMC - Vivado Hardware Manager DDRMC Write Calibration Margins Not Fully Captured in Left Aligned Chart Mode N/A N/A
76067 Versal ACAP DDRMC - Vivado Hardware Manager DDRMC Calibration Status Does not Show Any Calibration Margins when Calibration is Successful N/A N/A
76108 Versal ACAP DDRMC - LPDDR4x Power Estimates Not Captured in XPE N/A N/A
76109 Versal ACAP DDRMC - Multi-Rank DDR4 Designs Not Driving CK or CKE for the Second Rank in Simulation N/A N/A
76059 Versal ACAP DDRMC - DDR4 and LPDDR4/x PCB Simulation Support Article N/A N/A
76040 Versal ACAP DDRMC - DDR4 Intermittent CAL_DONE Failure Asserted when ECC and CA Parity are Enabled for Unbuffered Memory Topologies N/A N/A
76117 Versal ACAP DDRMC - DDR4 RESET_N Voltage Level Mismatch Analysis N/A N/A
76254 Design Advisory for Versal DDRMC - Pinouts Generated with User Specified DQS Byte Swaps for LPDDR4 and x8 or x16 DDR4 Component Interfaces Might Contain Errors Requiring PCB Changes N/A N/A
76283 Versal ACAP DDRMC - DDRMC XPLL Expectations and User LOC Constraint Interactions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
76181 Design Advisory Master Answer Record for Versal ACAP Devices N/A N/A
AR# 75764
Date 07/27/2021
Status Active
Type Release Notes
Devices
Tools
IP
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