General Description: Why does the XPLA1 ISP Demo Board CPLD function improperly?
The on-board clock circuit on the ISP demo board produces a clock with rise and fall times that are slower than those specified in the data sheet. This can cause improper clocking within the part, causing unpredictable behavior.
The slow rise/fall time is due to a termination resistor on the board, R2, which provides termination if an external clock is used for the board. This resistor should be removed from the board if the on-board clock circuit is being used.