Xilinx CPLDs consist of the following families: XC9500, XC9500XL, XC9500XV, CoolRunner XPLA3, and CoolRunner-II.
Solution
All Xilinx CPLDs are programmable via JTAG (often referred to as "in-system programming"). A Xilinx CPLD can be programmed on the board via JTAG, or programmed by a desktop programmer or ATE and installed on a board at a later time. The file used for programming is called a JEDEC file and has a ".JED" file extension.
This Answer Record discusses the requirements for programming using JTAG with a device on a board. For information regarding desktop programmers and third-party programmers, see: http://www.xilinx.com/support/programr/dev_sup.htm
To program a Xilinx device in-system, the JTAG pins must be accessible. When laying out the board, ensure that a header is available that is compatible with the appropriate Xilinx programming cable:
Parallel Cable III: Provide JTAG pins using standard 0.025 inch square male pins. Parallel Cable IV: Refer to the Parallel IV Cable Data Sheet, available in the "Configuration Solutions -> Configuration Hardware" section of: http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
The software used for programming CPLDs is called iMPACT, and it is available in all versions of ISE. iMPACT is also freely downloadable from the WebPACK site at: http://www.xilinx.com/ise/webpack
Obsolete Philips XPLA devices (XPLA1/enhanced and XPLA2) used a program called XPLA Programmer. This software is also available for download from the same WebPACK location. For more information on downloading software for these obsolete devices, refer to (Xilinx Answer 12342).