AR# 75894


2020.2 - Zynq UltraScale+ MPSoC VCU - Patches for the Zynq UltraScale+ MPSoC VCU TRD 2020.2 for a ZCU106 board


This answer record contains documentation on device-tree and kernel patches required for the Zynq UltraScale+ MPSoC VCU TRD on top of the release PetaLinux BSP for a ZCU106 board.

It contains examples of the ideal Device Tree for some standard video pipelines implemented in VCU TRD designs and kernel patches required to create the TRD BSP for the Zynq UltraScale+ MPSoC VCU TRD 2020.2 for a ZCU106 board.

For additional technical help, please post to the Xilinx Video Forums, Xilinx Embedded Linux Forums, or contact Xilinx Technical Support.


This documentation is intended to explain the changes required to create the Zynq UltraScale+ MPSoC VCU TRD 2020.2 BSP for a ZCU106 board from the release PetaLinux BSP.

Note: The VCU TRD BSP has all of the changes in place and relevant system-user.dtsi patches. Please refer to the build flow wiki for 2020.2 VCU TRD

This Documentation is required to understand the changes which must be made on top of the auto-generated device-tree to create the media pipelines on VCU TRD designs.

This information is detailed in the attached PDF document.


Associated Attachments

Name File Size File Type
VCU_TRD_2020.2_Device_Tree_and_Kernel_Changes.pdf 557 KB PDF

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AR# 75894
Date 03/22/2021
Status Active
Type Documentation Changes
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