AR# 75975

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Alveo - XRT - DFX two-stage platforms must program the shell partition before running an application

Description

This is a known issues article for the DFX-2RP platforms.

DFX two-stage platforms consist of both a base and shell partition.

See https://xilinx.github.io/XRT/master/html/platforms_partitions.html for an overview of Alveo platforms.

Prior to running an application on DFX-2RP two-stage platforms, it is necessary to first program the shell partition on the card, or else the application will fail to detect the shell and will not run.

The following platforms are DFX two-stage:

  • xilinx_u250_gen3x16_xdma_3_1_202020_1

Solution

For DFX-2RP platforms, it is necessary to not only flash the base partition, but also to program the shell partition prior to running an application.

 

To flash the base partition, see the “Installing the Deployment Software” section in (UG1301) V1.7

Once flashed, the base partition is persistent after cold and warm reboots and does not need to be reprogrammed. 

 

The shell partition is not persistent and needs to be reloaded after both a cold and warm reboot.  It does not need to be reloaded after running an application.

To program the shell partition, use the following command:

$ sudo /opt/xilinx/xrt/bin/xbmgmt partition --program --name <shell_name> --card <card_bdf>

To obtain the card_bdf and shell_name options, see Appendix D “Obtaining xbmgmt Command Options” in (UG1301) V1.7.

To validate that you have successfully loaded the shell, follow the instructions in the "xbutil validate" section in (UG1301) V1.7.

In addition, you can run the following command, explained in the section “Running xbmgmt partition” in (UG1301) V1.7, to display and confirm that the base and shell partitions are running on the FPGA.

$ sudo /opt/xilinx/xrt/bin/xbmgmt partition --scan

If you have successfully loaded the shell partition, an output showing both the base and shell partitions similar to the one below will be displayed.

Card [0000:af:00.0]
    Partitions running on FPGA:
        xilinx_u250_gen3x16_base_3
            logic-uuid:
            48810c9d17860ef53e9e529e8b14ce39
            interface-uuid:
            695718ec21a232e45e1afcb4e558e11f
        xilinx_u250_gen3x16_xdma_shell_3_1
            logic-uuid:
            bd5fb8abab266c3265918257b5048e88
            interface-uuid:
            f2f6c5e1273e78948f2c4806221462f2

 

AR# 75975
Date 01/11/2021
Status Active
Type Known Issues
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