AR# 76059

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Versal ACAP DDRMC - DDR4 and LPDDR4/x PCB Simulation Support Article

Description

Introduction

The purpose of this Answer Record is to consolidate all of the information required for PCB designers to simulate Versal DDRMC DDR4, LPDDR4, and LPDDR4x interfaces.

The Description section includes information usable regardless of the interface type and interface specific information is found in the Solution section. The Description section includes information on HyperLynx DDRx simulations, IBIS Models, S-Parameters, overall simulation guidance, and other useful information. The Solution section breaks down the details regarding the configuration settings and IBIS models for every supported memory topology, the default IP constraints, and system clock constraints.

Each Versal DDRMC configuration has default settings for the ACAP device and the Memory device. These are manifested in the various Configuration Details and Default I/O Constraints tables in the Solution section. The same type of default configuration details are also captured in the default IBIS models used by the DDRMC as seen in the IBIS Models for Simulation tables. These are the validated settings from characterization which guarantee Versal DDRMC performance across silicon process corners and data sheet operation.

Additionally, these settings were validated on boards designed following the guidelines in (UG863). Any deviation from the default I/O constraints, memory settings, or excursions from the PCB level guidance in (UG863) might result in hardware failures unless they have been validated through system level channel signal integrity simulations.

Depending on the memory interface type there will be a default set of input System Clock constraints. These constraints can be changed from their defaults to match the specific hardware implementation but must meet the requirements in (AM010), (UG863), and the respective Versal data sheet I/O standard voltage and MMCM requirements.

Simulation Guidance

When setting up PCB level memory interface simulations there might be different assumptions regarding memory controller behavior which need to be defined in the tools. Here are the behaviors for the Versal DDRMC:

  • Write VREF levels are fixed as per the memory configuration and are used across all byte lanes
  • Read VREF levels are fixed as per the memory configuration and are used across all byte lanes
  • The controller has full Write/Read DQS to CK leveling
  • The controller has full Write/Read per bit DQS to DQ/DM deskew
  • The ODT settings are fixed as per the memory configuration
  • DDR4 does support 2T operating modes for the Command/Address/Control bus and this can be configured in the NoC DDRMC GUI
  • Only the IBIS models called out in the Solution section should be used for simulation
  • IBIS models are intended to be lumped elements and NOT distributed

Always Probe Reads at the ACAP Die

Due to the long package routing found in Versal ACAP devices, the Read waveforms must always be evaluated at the ACAP die. Probing at the ACAP balls will always have suboptimal results. 

Methods for probing at the die depend on the simulation software.  Siemens (formerly Mentor) has a Knowledge Base article (registration required) which describes how to do this.  For HyperLynx DDRx VX.2.4 and later there is an option in the Simulation Options page to set the Measurement Location at the controller die.

IBIS Models

After a Versal DDRMC interface has been generated and the block design synthesized it can be placed in an I/O triplet.  After it is placed, the IBIS models for that specific memroy configuration can be exported via the GUI or a Tcl command.

Below is a screenshot of the GUI method:

 


 

When the Export IBIS Model GUI is open there are options for Include all models and Disable per pin modeling as shown below:

 


 

If Include all models is disabled then only the IBIS models required for the placed design are included in the export. When this option is enabled then all Versal IBIS models are included, which results in a much larger file size.

If Disable per pin modeling is left unchecked then the package parasitics for each of the used pins in the design are included in the IBIS export.

For instances where S-Parameters will be used for package modeling, the Disable per pin modeling option must be enabled.

To export the IBIS models with a Tcl command use the following syntax:

write_ibis /path/to/output/filename.ibs

S-Parameter Models

S-Parameter models for the power and ground pins on Versal devices are hosted here:

https://www.xilinx.com/member/versal_si_pi_models.html

S-Parameter models for the XPIO pins on Versal devices are hosted here:

https://www.xilinx.com/member/versal_selectio_ibis_models.html

HyperLynx DDRx Timing Models

A ZIP file containing HyperLynx DDRx Timing Models for Versal DDR4 and LPDDR4 interfaces is attached to this Answer Record.

The timing models do not define every possible timing parameter, and in these instances the default values can be used.

Currently only DDR4 3200 and LPDDR4 4266/3733 are available. See versal_hyperlynx_ddrx_timing_models.zip at the bottom of this Answer Record.

Tutorials

DDR4 and LPDDR4 Timing Models for Hyperlynx DDRx Wizard in Versal ACAPs

A tutorial which shows how to use the HyperLynx DDRx timing models.

Obtaining and Verifying Versal ACAP Memory Pinouts

A tutorial which shows how to generate memory interface pinouts and validate them through the tools.

Additional Resources

(AM010) Versal ACAP SelectIO Resources Architecture Manual
(PG313) Versal ACAP Programmable Network on Chip and Integrated Memory Controller Product Guide
(UG863) Versal ACAP PCB Design User Guide
(DS956) Versal Prime Series Data Sheet: DC and AC Switching Characteristics
(DS957) Versal AI Core Series Data Sheet: DC and AC Switching Characteristics

Solution

DDR4 PCB Simulation Collateral Details

 

DDR4 Configuration Details per Topology

DDR4 Configuration ACAP Drive Strength ACAP ODT ACAP Slew ACAP Read VREF  DDR4 Rtt(nom)  DDR4 Rtt(park)  DDR4 Drive Strength  DDR4 Write VREF
Component Interfaces
Components 40-Ohms 40-Ohms Fast 0.88V 40-Ohms N/A 34-Ohms 0.88V
DDP Deep Components 40-Ohms 40-Ohms Fast 0.88V 40-Ohms 40-Ohms 34-Ohms 0.97V
UDIMM/SODIMM Interfaces
1 Rank 1 Slot UDIMM/SODIMM 40-Ohms 40-Ohms Fast 0.94V 40-Ohms N/A 34-Ohms 0.93V
2 Rank 1 Slot UDIMM/SODIMM 40-Ohms 40-Ohms Fast 0.98V 120-Ohms 60-Ohms 34-Ohms 0.93V
RDIMM Interfaces
1 Rank 1 Slot RDIMM 40-Ohms 40-Ohms Fast 0.94V 40-Ohms N/A 34-Ohms 0.93V
2 Rank 1 Slot RDIMM 40-Ohms 40-Ohms Fast 0.98V 120-Ohms 60-Ohms 34-Ohms 0.93V
1 Rank 2 Slot RDIMM 40-Ohms 40-Ohms Fast 1.0V 60-Ohms 40-Ohms 34-Ohms 0.97V
2 Rank 2 Slot RDIMM 40-Ohms 60-Ohms Fast 0.98V 240-Ohms 60-Ohms 34-Ohms 1.0V
LRDIMM Interfaces
2 Rank 1 Slot LRDIMM 40-Ohms 40-Ohms Fast 0.94V 40-Ohms N/A 34-Ohms 0.93V
4 Rank 1 Slot LRDIMM 40-Ohms 40-Ohms Fast 0.94V 40-Ohms N/A 34-Ohms 0.93V
2 Rank 2 Slot LRDIMM 40-Ohms 40-Ohms Fast 1.0V 60-Ohms 40-Ohms 34-Ohms 0.97V



DDR4 IBIS Models for Simulation

DDR4 Signal Group IBIS Model
Clock, Command, Address, Control XP_SSTL12_F_OUT40
DQ, DQS, DM/DBI XP_POD12_F_OUT40_IN40
XP_POD12_F_OUT40_IN60 only for Dual Rank Dual Slot RDIMMs
reset_n XP_LVCMOS12_S_8


DDR4 Default I/O Constraints


The following table describes the IP generated default constraints for the DDR4 DDRMC.

 

Signal Groups Constraint Value
Clock, Command, Address, Control IOSTANDARD SSTL12 or DIFF_SSTL12
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
DQ, DQS, DM/DBI IOSTANDARD POD12 or DIFF_POD12
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
EQUALIZATION EQ_LEVEL2
OFFSET_CNTRL CNTRL_NONE
ODT RTT_40
reset_n IOSTANDARD LVCMOS12
DRIVE 8


DDR4 Default System Clock Constraints


The following table describes the IP generated default constraints for the DDR4 DDRMC input System Clock. 

These constraints are allowed to be modified to match the clock generator, input bank I/O standard, and required voltage levels. 

See the respective Versal Data Sheet, (AM010), (PG313), and (UG863) for more details on DDRMC input system clock expectations.

Constraint Value
IOSTANDARD LVDS15
EQUALIZATION EQ_LEVEL2
DC_BIAS DC_BIAS_0

 

LPDDR4 PCB Simulation Collateral Details

LPDDR4 and LPDDR4x Power Supply Levels

 

Interface Type VCCO VDDQ VDD2
LPDDR4 1.1V 1.1V 1.1V
LPDDR4X 1.2V 0.6V 0.6V


LPDDR4 Configuration Details per Topology

 

LPDDR4 Configuration ACAP Drive Strength ACAP ODT ACAP Slew ACAP Read VREF PDDS
MR3 OP[5:3]
DQ ODT
MR11 OP[2:0]
CA ODT
MR11 OP[6:4]
SoC ODT
MR22 OP[2:0]
VREF(CA)
MR12 OP[5:0]
VREF(DQ) MR14[5:0]
Single Rank Component 40-Ohms 40-Ohms FAST 16.6% VCCO 40-Ohms 48-Ohms 48-Ohms 40-Ohms 27.2% VDD2 22% VDDQ
Dual Rank Component 40-Ohms 40-Ohms FAST 16.6% VCCO 40-Ohms 48-Ohms 48-Ohms 40-Ohms 27.2% VDD2 22% VDDQ



LPDDR4 Pin Efficient Configuration Details

 

LPDDR4 Configuration ACAP Drive Strength ACAP ODT ACAP Slew ACAP Read VREF PDDS
MR3 OP[5:3]
DQ ODT
MR11 OP[2:0]
CA ODT
MR11 OP[6:4]
SoC ODT
MR22 OP[2:0]
VREF(CA)
MR12 OP[5:0]
VREF(DQ) MR14[5:0]
Single Rank Component 40-Ohms 40-Ohms FAST 16.6% VCCO 40-Ohms 48-Ohms 48-Ohms 40-Ohms 22% VDD2 22% VDDQ



LPDDR4 IBIS Models for Simulation

LPDDR4 Signal Group IBIS Model
Clock, Address, and Control XP_LVSTL_11_F_OUT40_VOH50
DQ, DQS, DM/DBI XP_LVSTL_11_F_OUT40_IN40_VOH50
reset_n XP_LVSTL_11_F_OUT40_VOH50


LPDDR4 Default I/O Constraints

The following table describes the IP generated default constraints for the LPDDR4 DDRMC.

 

Signal Groups Constraint Value
Clock, Address, and Control IOSTANDARD LVSTL_11 or DIFF_LVSTL_11
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
VOH 50
DQ, DQS, DM/DBI IOSTANDARD LVSTL_11 or DIFF_LVSTL_11
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
EQUALIZATION EQ_LEVEL3
OFFSET_CNTRL CNTRL_NONE
ODT RTT_40
VOH 50
reset_n IOSTANDARD LVSTL_11
SLEW FAST



LPDDR4 Default System Clock Constraints


The following table describes the IP generated default constraints for the LPDDR4 DDRMC input System Clock. 

These constraints are allowed to be modified to match the clock generator, input bank I/O standard, and required voltage levels. 

See the respective Versal Data Sheet, (AM010), (PG313), and (UG863) for more details on DDRMC input system clock expectations.

Constraint Value
IOSTANDARD DIFF_LVSTL_11
EQUALIZATION EQ_LEVEL3
ODT RTT_NONE

 

LPDDR4X PCB Simulation Collateral Details

 

LPDDR4 and LPDDR4x Power Supply Levels

 

Interface Type VCCO VDDQ VDD2
LPDDR4 1.1V 1.1V 1.1V
LPDDR4X 1.2V 0.6V 0.6V


LPDDR4x Configuration Details

 

LPDDR4x Configuration ACAP Drive Strength ACAP ODT ACAP Slew ACAP Read VREF PDDS
MR3 OP[5:3]
DQ ODT
MR11 OP[2:0]
CA ODT
MR11 OP[6:4]
SoC ODT
MR22 OP[2:0]
VREF(CA)
MR12 OP[5:0]
VREF(DQ)
MR14[5:0]
Single Rank Component 40-Ohms 40-Ohms FAST 12.5% VCCO 40-Ohms 48-Ohms 48-Ohms 40-Ohms 26.3% VDD2 26.3% VDDQ
Dual Rank Component 40-Ohms 40-Ohms FAST 12.5% VCCO 40-Ohms 48-Ohms 48-Ohms 40-Ohms 26.3% VDD2 26.3% VDDQ


LPDDR4x IBIS Models for Simulation

 

LPDDR4 Signal Group IBIS Model
Clock, Address, and Control XP_LVSTL06_12_F_OUT40
CKE XP_SSTL12_F_OUT40
DQ, DQS, DM/DBI XP_LVSTL06_12_F_OUT40_IN40
reset_n XP_LVCMOS12_S_8


LPDDR4x Default I/O Constraints


The following table describes the IP generated default constraints for the LPDDR4X DDRMC.

 

Signal Groups Constraint Value
Clock, Address, and Control IOSTANDARD LVSTL06_12 or DIFF_LVSTL06_12
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
DQ, DQS, DM/DBI IOSTANDARD LVSTL06_12 or DIFF_LVSTL06_12
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
EQUALIZATION EQ_LEVEL3
OFFSET_CNTRL CNTRL_NONE
ODT RTT_40
CKE IOSTANDARD SSTL12
SLEW FAST
OUTPUT_IMPEDANCE RDRV_40_40
reset_n IOSTANDARD LVCMOS12
DRIVE 8


LPDDR4x Default System Clock Constraints


The following table describes the IP generated default constraints for the LPDDR4X DDRMC input System Clock. 

These constraints are allowed to be modified to match the clock generator, input bank I/O standard, and required voltage levels. 

See the respective Versal Data Sheet, (AM010), (PG313), and (UG863) for more details on DDRMC input system clock expectations.

Constraint Value
IOSTANDARD DIFF_LVSTL06_12
EQUALIZATION EQ_LEVEL3
ODT RTT_NONE

 

Revision History:

  • 02/12/2021 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
versal_hyperlynx_ddrx_timing_models.zip 593 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
75764 Versal ACAP Programmable Network on Chip and Integrated Memory Controller - IP Release Notes and Known Issues N/A N/A
AR# 76059
Date 02/12/2021
Status Active
Type General Article
Devices
Tools
IP
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