AR# 76156


2020.2.2 Vivado Implementation - ERROR: [DRC RTSTAT-6] Partial route conflicts


In Vivado 2020.2.2, I get the following error during a DRC check when using a XCVM1802 device:

ERROR: [DRC RTSTAT-6] Partial route conflicts: 5 net(s) have a partial conflict. The problem bus(es) and/or net(s) are RAM_reg_192_255_14_14/SP/O, RAM_reg_128_191_2_2/SP/O, p_0_out1_out[9], p_0_out1_out[12], and wa_IBUF.

My design was implementing successfully in previous builds.


This has been identified as a known issue in the 2020.2.2 release when using an XCVM1802 device.

As a work-around, use the following Tcl command before running Implementation:

set_param route.enableBuildNodeGraphFromOfflinedFiles false
AR# 76156
Date 02/16/2021
Status Active
Type General Article
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