AR# 76169

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Zynq UltraScale+ MPSoC Controller for PCI Express (Vivado 2021.1) - System Example Design with ZCU102 PS-PCIe as Root Complex and Intel SSD 750 Series NVMe Device as an Endpoint

Description

This answer record provides a System Example Design with ZCU102 PS-PCIe as Root Complex and an Intel SSD 750 Series NVMe Device as an Endpoint in a downloadable PDF to enhance its usability.

Answer Records are Web-based content that are frequently updated as new information becomes available.

Visit this answer record to obtain the latest version of the PDF.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This document shows how to design and configure the Zynq UltraScale+ MPSoC Controller for PCI Express as Root Complex with NVMe (non volatile memory endpoint) device Intel SSD 750 Series as an endpoint.

The document also walks through the steps for generating a PetaLinux image to boot Linux on the Zynq UltraScale+ MPSoC.

Below are the list of topics described in the document:

  • Configuration of PS-PCIe
  • Configuring the Kernel for PCIe and NVMe hosting on the Zynq UltraScale+ device
  • Configuring the Rootfs with PCIe and NVMe utilities
  • Building the project from the configured components
  • Packaging the project together with the bitstream.
  • PCIe NVMe simple write and read operation and speed test

Revision History:

  • 03/25/2021: Initial Release

Attachments

Associated Attachments

Name File Size File Type
Xilinx_Answer_76169_ZCU102_PS_PCIe_NVMe.pdf 1 MB PDF
AR# 76169
Date 03/25/2021
Status Active
Type General Article
IP
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