AR# 76182

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Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - PS LPDDR4 DRAM memory errors for data rates at/below 1600 MT/s

Description

This Design Advisory covers the Zynq UltraScale+ MPSoC/RFSoC PS memory controller.

At LPDDR4 operating data rates at and below 1600 MT/s, memory data and calibration errors might occur.

This issue impacts Micron LPDDR4 DRAM topologies generated in versions from including Vivado 2019.2 and prior to Vivado 2021.1, and Hynix/Samsung LPDDR4 DRAM designs in versions prior to 2021.1.

Solution

This issue is caused by Write Latency Set (WLS) in the PSU_DDR_PHY_MR2_WLS/PSU_DDRC_INIT3_EMR registers being incorrectly set to use Set "B" in MR2, causing a mismatch with the intended Set "A" write latency value.

Also, DRAM ODT is not disabled at rates at and below 1066 MT/s.

To work around this issue, increase the PS LPDDR4 actual interface data rate to above 1600 MT/s (800 MHz clock rate).

A patch for Vivado 2020.1 is available below.

This issue is planned to be fixed starting in the Vivado 2021.1 release.

Revision History:

  • 04/13/21 - Added 2020.1 patch
  • 03/07/21 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR76182_CR1087762_vivado_2020_1_preliminary_rev1.zip 5 MB ZIP
AR# 76182
Date 04/23/2021
Status Active
Type Design Advisory
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