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AR# 7621

CPLD CoolRunner XPLA3 CoolRunner-II - Decoupling recommendations


What recommendations exist for CoolRunner/-II/XPLA3) devices regarding decoupling?


Edge rates of CoolRunner parts can be sub 2 nS speeds. Decoupling is a priority, as is the application of good design technique such as the use of ground and power planes, limited trace length, and signal termination.

Always decouple every VCC pin. The VCC structure of the CoolRunner devices is such that VCC pins power different portions of the device; decoupling only a portion of the pins carries the risk of not decoupling an integral part of the device.

For a "rule of thumb minimum," place a .01 uF capacitor on each VCC pin. This capacitor should be a surface-mount, ceramic chip type capacitor placed as physically close to the VCC pin as possible.

For other common questions, refer to the CPLD FAQ: (Xilinx Answer 24167).

AR# 7621
Date 12/15/2012
Status Active
Type General Article