You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
CPLD XPLA1 - Is there hysterisis on inputs or clock pins?
Keywords: XPLA, CoolRunner, XPLA1, input, hysterisis, clock, pins
In the XPLA1 family, is there any hysterisis on any of the input or clock pins?
The only pin that has hysterisis is the TCK (JTAG) pin, as hysterisis on input and clock pins causes undesirable delays.
Was this Answer Record helpful?