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  1. Xilinx - All Programmable
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  3. AR# 7640: CPLD XPLA1 - The XPLA fitter does not allow a pin associated with an asynchronous clock to be used as a standard I/O

AR# 7640

CPLD XPLA1 - The XPLA fitter does not allow a pin associated with an asynchronous clock to be used as a standard I/O

Description

My fitter does not allow me a pin associated with an asynchronous clock signal to be used as a standard I/O. Why?

Solution

If an asynchronous global clock is driven by an internal product term expression, the global clock pin associated with this clock is driven by the output macrocell. This excludes the use of the pin for any other function.

AR# 7640
Date 05/14/2014
Status Archive
Type General Article