General Description: What are the differences between ABEL and PHDL?
PHDL (formerly Philips Hardware Description Language) is a sub-set of ABEL.
Most PHDL designs should compile without modification (except for changing the file extension to .abl) in Xilinx Project Navigator. The only exception to this are the dot extensions .X1 and .X2 that are supported in PHDL to support the hardware XOR function in CoolRunner XPLA2 (960 and 320 macrocell devices) CPLDs.
The following table shows ABEL features that are either ignored or not supported in PHDL:
ABEL and PHDL Differences
It is important to note that the PHDL compiler will do syntax checking on signals that have register attributes (reg, reg_d, reg_g, reg_jk, reg_sr, and reg_t) to insure that these signals have a clock (.clk) assignment and a consistent input assignment (.d for reg_d, .t for reg_t). If a signal with a register attribute does not have clock assignment or has an inconsistent input assignment statement, an error is generated. This syntax- checking with register attributes is not done in ABEL.
Also note that CoolRunner CPLDs do not have an inverter between the macrocell and the output pin. Therefore, the INVERT attribute results in the inverter being emulated in the equations for the register input, and equations for AR and AP are swapped.
However, since CoolRunner 22V10s do have an inverter between the macrocell and the output pin, the INVERT attribute is handled as expected. The INVERT attribute has no meaning for combinatorial signals.