We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7703

TRCE/Timing Analyzer 2.1i: Clock DLLs with period constraints appear in the reports as if they are not constrained


Keywords: DLL, CLKDLL, period, constraint

Urgency: Standard

General Description:
Period constraints on clock DLLs get pushed to the appropriate clock output port
on the DLL. 'Report Paths not Covered by Timing Constraints' report in Timing
Analyzer now reports the DLL as not being constrained. The DLL is in fact
constrained, but the actual constraint gets pushed through the DLL, so Timing
Analyzer thinks that the DLL is not constrained.



Ignore the paths covered by 'constrained' DLLs.
AR# 7703
Date 07/11/2001
Status Archive
Type General Article
Page Bookmarked