We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7709

2.1i Virtex Map - MAP uses the incorrect JF setting for a CLKDLLHF


Keywords: JF MAP

Urgency : Standard

General Description:
A high freqency DLL should have a JF (jitter) setting of 0xFFF0.
A regular DLL shoulf have a JF setting of 0xC080.
Instances have been seen where MAP assigns a CLKDLLHF 0xC080
instead of 0xFFF0 even though it is checked as High Frequency in FPGA Editor.


This problem is fixed in the latest 2.1i Service Pack available at:
AR# 7709
Date 07/20/2001
Status Archive
Type General Article
Page Bookmarked