HDL design modules which have constants as inputs may output unknown values during timing simulation. In the back-annotated simulation file, these inputs are hanging, hence the simulation results unknown states. This is a result of ngdanno becoming confused when a slice both generates and consumes a pwr/gnd signal.
Workaround is to preclude the .ngm file from being read by ngdanno. This can be accomplished by deselecting 'Correlate Simulation Data to Input Design' under Simulation Options in Design Manager.