General Description: FPGA Express 3.3 and older: Instantiated input or output flops with clock enables (IFDX, IFDXI, OFDX, OFDXI; these are primitives in the XC4000 architecture) get written to netlist as IFD or OFD. IFD and OFD do not include a clock enable pin, so a pin mismatch error occurs in NGDBUILD:
ERROR:NgdHelpers:312 - logical block "my_input_reg" of type "IFD" is unexpanded.
Solution
Instead of instantiating the IFDX or IFDXI, allow FPGA Express to infer these components. Here is an example that will work, provided D is a chip input, RST is a global reset that will be connected to the STARTUP block, and Merge I/O is set to TRUE (default).
VHDL Example:
my_IFDX:process (CLK, RST) begin if (RST='1') then Q <= '0'; --change to '1' for set flip flop (IFDXI/OFDXI) elsif (CLK'event and CLK='1') then if (CE='1') then --infers clock enable Q <= D; end if; end if; end process;
Verilog Example:
always @(posedge CLK or posedge RESET) begin if (RESET) DOUT = 1'b0; //change to '1' for set flip flop (IFDXI/OFDXI) else if (ENABLE) //infers clock enable DOUT = DIN; end
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AR# 7727
Date
10/03/2008
Status
Archive
Type
General Article
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