AR# 7822: Exemplar - How do I infer an SRL16 for Virtex/-E devices in HDL (Verilog/VHDL)?
Exemplar - How do I infer an SRL16 for Virtex/-E devices in HDL (Verilog/VHDL)?
Keywords: SRL, inferring, 1999, 1e
General Description: The latest version of LeonardoSpectrum (1999.1e at the writing of this answer record) supports the inferring of SRL16s for Virtex designs. The following two variables control this:
- The first variable enables SRL mapping (default: TRUE): set virtex_map_srl true
- The second variable packs the SRL into a single slice (default: TRUE): set virtex_map_srl_pack true
NOTE: - In Synplify, the SRL is mapped by default when possible. - Synplify currently does not map to an SRL when the pipeline (cycle) is two and under. This will be fixed in the next software release.
The following coding styles work for both Exemplar and Synplify.
VHDL Example Design of SRL16 Inference for Virtex
NOTE: This design infers sixteen SRL16s with a 16-pipeline delay.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;