General Description:
How do I infer SRL16 in Virtex/-E designs?
The latest version of Synplify infers SRL16 by default.
Refer to (Xilinx Answer 7822) for VHDL/Verilog code which results in SRL16 inference:
http://www.xilinx.com/techdocs/7822.htm.
AR# 7833 | |
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Date | 12/15/2012 |
Status | Active |
Type | General Article |