AR# 7859: 2.1i COREGEN VERILOG, VHDL: How to extract the CORE Generator Verilog and VHDL behavioral simulation models
AR# 7859
2.1i COREGEN VERILOG, VHDL: How to extract the CORE Generator Verilog and VHDL behavioral simulation models
Description
Keywords: vhdl, verilog, simulation
Urgency: standard
General Description: How to extract the CORE Generator Verilog and VHDL behavioral simulation models
Solution
1. The 2.1i CORE Generator does not generate a .VHD or .V file for each core in the 2.1i release. Instead, it creates a .VHO (for VHDL) or .VEO (for Verilog) template file containing the code snippets required to integrate the core into a higher level design block's behavioral simulation netlist.
2. Before any behavioral simulation of a core can be done, you must :
- run the get_models utility to extract the models into a separate source library,
- analyze the library, if required by your simulator, to a library named "xilinxcorelib". (VHDL and compiled Verilog simulators)
- set your simulator to point to the extracted (and analyzed) library
Please refer to the Design Flows chapter of the CORE Generator User Guide (available from within the CORE Generator under Help->Online Documentation) for more details. The latest version is accessible at: http://support.xilinx.com/support/techsup/journals/coregen/2.1i/ug2_1a.pdf The details are documented in the HDL Design Flows section of the last chapter.