We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7859

2.1i COREGEN VERILOG, VHDL: How to extract the CORE Generator Verilog and VHDL behavioral simulation models


Keywords: vhdl, verilog, simulation

Urgency: standard

General Description:
How to extract the CORE Generator Verilog and VHDL behavioral simulation models


1. The 2.1i CORE Generator does not generate a .VHD or .V
file for each core in the 2.1i release.
Instead, it creates a .VHO (for VHDL) or .VEO (for Verilog) template file
containing the code snippets required to integrate the core into a
higher level design block's behavioral simulation netlist.

2. Before any behavioral simulation of a core can be done,
you must :

- run the get_models utility to extract the models into a separate source

- analyze the library, if required by your simulator, to a library named "xilinxcorelib".
(VHDL and compiled Verilog simulators)

- set your simulator to point to the extracted (and analyzed) library

Please refer to the Design Flows chapter of the CORE Generator User Guide
(available from within the CORE Generator under Help->Online Documentation)
for more details. The latest version is accessible at:
The details are documented in the HDL Design Flows section of the last chapter.

AR# 7859
Date 08/31/2001
Status Archive
Type General Article
Page Bookmarked