Virtex and Spartan devices require a 32-bit synchronization word (0xAA995566) before they will recognize configuration data. How do I determine whether the device has been synchronized?
There is no direct way to determine if a device is synchronized; however, this can be determined indirectly. Different techniques must be used depending upon the configuration mode.
Determining whether a device in a Serial Configuration mode is synchronized
If you suspect that the device is not properly synchronized, creative use of the LOUT register can indicate proper synchronization.
NOTE: Writing to the LOUT register is only valid in serial modes
The LOUT register is a pipeline register that transfers data to the DOUT pin. Inserting a small LOUT Write immediately after the synchronization word is loaded will allow you to determine whether the sync word was loaded properly. If it was, the device will recognize the LOUT Write packet, and data will appear on the LOUT pin.
There is a latency of 40 clock cycles between data being written to LOUT and data appearing on DOUT. If the sync word is not loaded properly, no packets will be recognized, and the DOUT pin will remain High.
The easiest way to use the LOUT register for debugging is to specify the "-g DebugBitstream:Yes" option in BitGen (Xilinx Answer 4219). This will produce a bit file with a LOUT Write after the sync word, and after each frame. However, the debug bitstream will be approximately 20% larger than the standard bitstream. If the increase in bitstream size makes the debug bitstream impractical for your application, LOUT writes can be inserted manually as follows.
Bitstream as produced by BitGen (separated by DWORDS for clarity):
FFFFFFFF AA995566 30008001 (CMD Write) ... ...
You can insert a packet for a LOUT Write -- before the first CMD Write -- into the RBT file:
FFFFFFFF AA995566 30010001 (Packet header for a LOUT Write with Word Count = 1) 00000000 (32 bits of data) 30008001 (First CMD Write) ... ...
NOTE: The "Bits:" field in the RBT file should be changed to reflect this increase in size. Do not manually edit the ".bit" file, as this might cause problems with PROMGen or the download tools.
This example will produce 32 0s on DOUT. While this example uses LOUT Writes to indicate whether the sync word is loaded, other LOUT Writes can be embedded in the bitstream for any reason at any point during configuration.
For a more in-depth discussion of the Virtex configuration format and explanation of configuration registers and packets, please refer to the Xilinx Application Note (Xilinx XAPP138): "Virtex FPGA Series Configuration and Readback".
Detecting synchronization in Master Serial mode In Master Serial Mode, there is an indirect way to determine whether the device is synchronized:
Early in the bitstream, a command that will change the frequency of the CCLK is loaded. The default speed is approximately 2 MHz, and the changed frequency is about 4 MHz. If you observe a change in the CCLK frequency early in the configuration process, you know that the device is synchronized. (This is because the synchronization word must be loaded in the device in order for any commands to be recognized and processed.)
Detecting synchronization in SelectMAP Mode In SelectMAP mode, you cannot use the LOUT Write because the DOUT pin (where the LOUT data is written to) becomes the BUSY signal when the MODE pins are set for SelectMAP. However, the FPGA Status register is available through the SelectMAP interface, and it can be used to gather the same information in a different way.
When an ABORT is issued, the FPGA drives out a status word onto the data lines. This status word contains information on synchronization. For details on the ABORT process, please refer to (Xilinx Answer 8520).