General Description: Leonardo Spectrum can map memory statements in Verilog or VHDL to the block RAMs on all Virtex devices.
The following is a list of details for block RAMs in Leonardo Spectrum:
- Virtex Block RAMs are completely synchronous. Both read and write operations are synchronous.
- Leonardo Spectrum infers the following Block RAM configuration: 1. Single-port RAMs or RAMs with both read and write on the same address. 2. Dual-port RAMs - RAMs with separate read and write addresses. (Write from Port A, Read from Port B)
- Leonardo Spectrum does not infer the following configurations: 1. Dual-port RAMs that read and write from both A and B ports. 2. Block RAMs that use the functionality of the RST and ENA pins.
Variables: Set the following variable to "false" if you do not want RAM extraction: (The default is TRUE.)
set extract_ram false
By default, RAMs that are mappable to block RAMs are mapped to block RAMs. You can disable mapping to block RAMs by setting the attribute block_ram to "false," as follows:
set_attribute -name block_ram -value false
In this case, the RAM is implemented using select RAMs if possible.
NOTE: - The variant of single-port RAM that is implemented using block RAMs cannot be implemented using select RAMs.
- Initializing inferred RAM in the HDL code is currently not supported. To do this, obtain the instance name of the RAM from Leonardo Spectrum's schematic viewer or from the EDIF netlist, and apply the INIT attribute in the UCF file. (The inferred RAMs are initialized to "0" (zero) by default.)
Verilog Example: (Tested in Leonardo Spectrum 1999.1f)