AR# 7949

FPGA Express 3.3: FPGA-buffermap-25 occurs when clock signal is connected to non-clock loads

Description

Keywords: FPGA, Express, Foundation, 25, BUFG, BUFGP, clock, drivers, buffer

Urgency: Standard

General Description:
FPGA Express 3.3 may report the following error:

Error: Buffer allocation detected possible drivers on the same net as clock input
'/virtex_clk-Optimized/clk'. (FPGA-buffermap-25)

This error may occur when a clock signal sources inferred flip flops and other non-clock
loads (combinatorial logic and/or black boxes). This been seen when FPGA Express
infers a clock buffer on this signal or when the user specifies a clock buffer via the
Express Constraints editor.

Solution

In any case, the workaround is to instantiate the clock buffer in your HDL code.
AR# 7949
Date 10/03/2008
Status Archive
Type General Article