UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 8006: Virtex-E CLKDLL - What is the input clock frequency range for Virtex-E CLKDLLs to be locked?

AR# 8006

Virtex-E CLKDLL - What is the input clock frequency range for Virtex-E CLKDLLs to be locked?

Description

What is the input clock frequency range for Virtex-E CLKDLLs to be locked?

Solution

For -6 parts: 

 

Min(Mhz) Max(Mhz) 

CLKDLL: 25 130 

CLKDLLHF: 60 260 

 

For -7 parts: 

 

Min(Mhz) Max(Mhz) 

CLKDLL: 25 160 

CLKDLLHF: 60 320

AR# 8006
Date 05/14/2014
Status Archive
Type General Article
Page Bookmarked