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Synopsys FPGA Compiler, M2.1i PAR: ERROR:Parsers:3 - Unable to parse "+" in line 4.
Keywords: par, parsers, parse, FPGA Compiler, Synopsys, sedif, %, + Urgency: Standard General Description: When running m2.1i PAR, you may get following error message. ERROR:Parsers:3 - Unable to parse "+" in line 4. ERROR:Par:51 - The .pcf file contains errors/warnings. PAR cannot proceed. This error message is saying that it found an illegal character "+" in the .pcf file. This error may occur if you have used Synopsys FPGA Compiler to generate your netlist and if you have also used Floorplanner. Synopsys FPGA Compiler may illegally write out .edif netlist with unusual net name such as: ) (net (rename &____return2956_2_ "%34%+%34%-return2956<2>") (joined (portRef A_2_ (instanceRef add_782_plus_plus)) (portRef S_2_ (instanceRef add_781_plus_plus)) ) The net name such as "%34%+%34%-return2956<2>" is illegal in EDIF. However, Xilinx implementation tools may not have a problem with it until PAR is run with these nets specified in the .pcf file.
One workaound is to re-synthesize your design using a different Synopsys compiler such as FPGA Express or FPGA Compiler II, then re-implement the design. However if you must use FPGA Compiler, then re-synthesize your code using following commands in your .synopsys_dc.setup file: define_name_rules rule1 -restricted "+\\-\"" -type cell -replace "#" define_name_rules rule2 -restricted "+\\-\"" -type net -replace "#" change_names -rules rule1 -verbose -hierarchy change_names -rules rule2 -varbose -hierarchy The above four lines should be added right after a line: "define_design_lib WORK -path ./WORK" These can also be placed in your run script after the "compile" command has been run. The newly created netlist should not contain any net names with unusual characters such as "%" or "+". Now, you should be able to implement your design without any problems.
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