AR# 8015

5.1i CORE Generator, Synopsis VSS - How do I compile the CORE Generator modules for VSS simulation?

Description


General Description:

How do I compile the CORE Generator library models for simulation in Synopsys VSS?

Solution


1. 2.1i only: Read the CORE Generator User Guide documentation (accessible from Help-> Online Documentation in the CORE Generator GUI) for instructions on extracting the models and setting up your library directory.



2. In your .synopsys_vss.setup file, you must declare a working directory called "xilinxcorelib". This is the library to which the CORE Generator models will be compiled.



For example:



xilinxcorelib : <path_to_directory>/xilinxcorelib



3. Be sure that your .synopsys_vss.setup file is in the same directory in which vhdlan is being run. Your .synopsys_vss.setup file must contain at least the following:



TIMEBASE = NS

TIME_RES_FACTOR = 0.01



WORK > DEFAULT

DEFAULT : .

xilinxcorelib : <path_to_directory>/xilinxcorelib



VHDL library to UNIX dir mappings



SYNOPSYS : $SYNOPSYS/packages/synopsys/lib

IEEE : $SYNOPSYS/packages/IEEE/lib



4. Compile each model using the following command line.



vhdlan -i -w xilinxcorelib <path_to_extracted_Coregen_libraries>/<filename>.vhd



2.1i IP Updates: See (Xilinx Solution #6250) for the compilation order to be used.



3.1i IP Updates: The required compiled order is documented in the following files in each 3.1i update:



$XILINX/verilog/src/XilinxCoreLib/verilog_analyze_order

$XILINX/vhdl/src/XilinxCoreLib/vhdl_analyze_order
AR# 8015
Date 07/28/2010
Status Archive
Type General Article