General Description: The following problems may be seen with the Verilog model for the 4K Constant Coefficient Multiplier core shipped in the 1.5 and 2.1i releases of the CORE Generator when simulating in Synopsys VCS or Cadence Verilog-XL:
1. The number of latency cycles may be incorrect, usually short by 1 cycle. 2. Race condition associated with transitioning of the output on a rising clock edge
The problems are similar to those found in the Virtex Dynamic Constant Coefficient Multiplier Verilog model as described in (Xilinx Solution #8020).
This problem is fixed in the C_IP4 IP release, which can be downloaded from: