UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8065

LogiCORE - How do I generate a Verilog or VHDL post-translate (post-NGDBuild) gate-level simulation netlist from a LogiCORE netlist?

Description

Keywords: CORE Generator, simulate, missing, model, structural, model

How do I generate a Verilog or VHDL post-translate (post-NGDBuild) gate-level simulation netlist from a LogiCORE netlist (e.g., the EDIF or NGC implementation netlist for a CORE Generator module)?

Solution

1

Follow these steps:

1. Generate an NGD file for the core as follows:

NOTE: File can be EDIF or NGC. i.e. corename.edn or corename.ngc.

ngdbuild -p <part_type> corename.ngc ---> Yields a file named "corename.ngd"

For example:

ngdbuild -p XC4VSX35ff668-10 bram2048x8.ngc ---> Yields a file named "bram2048x8.ngd"

(If you are using Xilinx Project Navigator, this is equivalent to running only the "translate" stage in the Process View, targeting an XC4VSX35ff668-10 part type.)

2. Generate a gate-level simulation netlist with NetGen as follows:

NOTE 1: You must generate the netlist in command line mode, and you MUST include the .ngd extension.
NOTE 2: If you are using an older version of the Xilinx software, you must use the commands listed below under Solution 2.

For example:

netgen -sim -ofmt verilog corename.ngd
netgen -sim -ofmt vhdl corename.ngd

3. If you are performing VHDL behavioral simulation and are substituting this new model for a CORE Generator module, you only need a component and instantiation block for both simulation and synthesis. The configuration snippet from the CORE Generator VHO file should be commented out. For example, for an 8-bit adder, the following block should be commented out:

-- synopsys translate_on
-- for all : myadder8 use entity XilinxCoreLib.C_ADDSUB_V1_0(behavioral)
-- generic map(
-- c_sinit_val => "0",
-- c_a_type => 0,
-- c_sync_enable => 0,
-- c_has_ainit => 0,
-- c_sync_priority => 1,
. . . (remaining generics omitted)
-- end for;

-- synopsys translate_on

4. If you are performing Verilog behavioral simulation and are substituting this new model for a CORE Generator module, you only need part of a module declaration and instantiation block for both simulation and synthesis. The library inclusion and part of the module declaration from the CORE Generator VEO file should be commented out. For example, for an add_sub core, the following block should be commented out:

// synopsys translate_off

`include "XilinxCoreLib/C_ADDSUB_V1_0.v"

// synopsys translate_on


// synopsys translate_off

C_ADDSUB_V1_0 #(
0,
"0000",
1,
16,
0,
0,
0,
1,
"0",
16,
1,
0,
.
.
.
1,
"0",
0,
1)
inst (
.A(A),
.B(B),
.C_IN(C_IN),
.Q(Q),
.CLK(CLK));

// synopsys translate_on

2

NOTE: If you are using an older version of the Xilinx software (less than 6.1i), you must use the following commands for Step 2.

2. Generate a gate-level simulation netlist with the appropriate translator (NGD2VHDL for a VHDL netlist, and NGD2VER for a Verilog netlist).

NOTE: You must generate the netlist in command line mode, and you MUST include the .ngd extension.

For example:

ngd2ver corename.ngd (Verilog)
ngd2vhdl corename.ngd (VHDL)
AR# 8065
Date Created 08/21/2007
Last Updated 04/16/2008
Status Archive
Type General Article