General Description:
CLKDLL is a clock delay-locked loop used to minimize clock skew. The simplest configuration of clockdll (BUFGDLL) can be inferred with a Xilinx-specific attribute in Synplify (Xilinx Solution 688).
Otherwise, CLKDLL needs to be instantiated as described below. For further information on CLKDLL usages, please reference (Xilinx XAPP132).
For an example on how to pass attribute to CLKDLL, please see (Xilinx Solution 11095). This solution illustrates DCM instantiation, but the attribute passing method is the same.
NOTE: Tested in Synplify 5.2.2a.
The example uses the default I/O standard (LVTTL). If using other I/O standards, instantiate the appropriate IBUFG_selectIO.
Verilog example
In this example, the ACLK's frequency is doubled and used inside and outside the chip. BCLK and OUTBCLK are connected in the board outside the chip.
`include "<path_to>/unisim.v"
module clock_test(ACLK, DIN, QOUT, BCLK, OUTBCLK, BCLK_LOCK, RESET);
input ACLK, BCLK;
input RESET;
input [1:0] DIN;
output [1:0] QOUT;
output OUTBCLK, BCLK_LOCK;
reg [1:0] QOUT;
IBUFG CLK_ibufg_A
(.I (ACLK),
.O(ACLK_ibufg)
);
BUFG ACLK_bufg
(.I (ACLK_2x),
.O (ACLK_2x_design)
);
IBUFG CLK_ibufg_B
(.I (BCLK), // connected to OUTBCLK outside
.O(BCLK_ibufg)
);
CLKDLL ACLK_dll_2x // 2x clock
(.CLKIN(ACLK_ibufg),
.CLKFB(ACLK_2x_design),
.RST(1'b0),
.CLK2X(ACLK_2x),
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLKDV(),
.LOCKED(ACLK_lock)
);
CLKDLL BCLK_dll_OUT // off-chip synchronization
(.CLKIN(ACLK_ibufg),
.CLKFB(BCLK_ibufg), // BCLK and OUTBCLK is connected outside the chip.
.RST(1'b0),
.CLK2X(OUTBCLK), //connected to BCLK outside
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLKDV(),
.LOCKED(BCLK_LOCK)
);
always @(posedge ACLK_2x_design or posedge RESET)
begin
if (RESET)
QOUT[1:0] <= 2'b00;
else if (ACLK_lock)
QOUT[1:0] <= DIN[1:0];
end
endmodule
VHDL example
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity CLOCK_TEST is
port(
ACLK : in std_logic;
-- off chip feedback, connected to OUTBCLK on the board.
BCLK : in std_logic;
--OUT CLOCK
OUTBCLK : out std_logic;
DIN : in std_logic_vector(1 downto 0);
RESET : in std_logic;
QOUT : out std_logic_vector (1 downto 0);
-- CLKDLL lock signal
BCLK_LOCK : out std_logic
);
end CLOCK_TEST;
architecture RTL of CLOCK_TEST is
component IBUFG
port (
I : in std_logic;
O : out std_logic);
end component;
component BUFG
port (
I : in std_logic;
O : out std_logic);
end component;
component CLKDLL
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
LOCKED : out std_logic);
end component;
-- Glock signals
signal ACLK_ibufg : std_logic;
signal BCLK_ibufg : std_logic;
signal ACLK_2x : std_logic;
signal ACLK_2x_design : std_logic;
signal ACLK_lock : std_logic;
begin
ACLK_ibufg : IBUFG
port map (
I => ACLK,
O => ACLK_ibufg
);
BCLK_ibufg : IBUFG
port map (
I => BCLK,
O => BCLK_ibufg
);
ACLK_bufg : BUFG
port map (
I => ACLK_2x,
O => ACLK_2x_design
);
ACLK_dll : CLKDLL
port map (
CLKIN => ACLK_ibufg,
CLKFB => ACLK_2x_design,
RST => '0',
CLK2X => ACLK_2x,
CLK0 => OPEN,
CLK90 => OPEN,
CLK180 => OPEN,
CLK270 => OPEN,
CLKDV => OPEN,
LOCKED => ACLK_lock
);
BCLK_dll_out : CLKDLL
port map (
CLKIN => ACLK_ibufg,
CLKFB => BCLK_ibufg,
RST => '0',
CLK2X => OUTBCLK,
CLK0 => OPEN,
CLK90 => OPEN,
CLK180 => OPEN,
CLK270 => OPEN,
CLKDV => OPEN,
LOCKED => BCLK_lock
);
process (ACLK_2x_design, RESET)
begin
if RESET = '1' then
QOUT <= "00";
elsif ACLK_2x_design'event and ACLK_2x_design = '1' then
if ACLK_lock = '1' then
QOUT <= DIN;
end if;
end if;
end process;
END RTL;
AR# 8144 | |
---|---|
Date | 12/15/2012 |
Status | Active |
Type | General Article |