AR# 8194


3.1i COREGEN - What's new in the 3.1i version of the Xilinx CORE Generator


Keywords: new, coregen

Urgency: hot

General Description:
What's new in the 3.1i version of the Xilinx CORE Generator


1. Faster startup times on all platforms.

2. Faster run times on Solaris (~1.5x)

3. New CORE Generator main GUI
- New, streamlined target family support display on main screen
- Streamlined links to related Xilinx Support web pages
- New user-editable Preference settings window (options for number of
projects to remember, path to web browser, path to PDF browser, always
point to last project, and automatically overwrite output files.
- New IP sorting capability available from new "View Cores" drop-down
menu allows you to display the Cores Catalog Alphabetically, by Function,
by Vendor, by Family, or by Type to allow you to easily locate cores that
you are interested in
- New streamlined Project Options window for designating Design Flows
- For HDL flows, .vho and .veo template files are generated by default when a
VHDL or Verilog design flow is selected
- Improved File Chooser dialogs

4. User-specified preferences are stored in .coregen.prf in the
user's home directory on UNIX platforms, and in the Windows registry on PC's:
Improved graphical busy status cues

5. New Foundation ISE support has been added (PC platforms only)

6. Newer versions of JAVA and SWING are supported (1.1.7b) / SWING 1.1.1

7. New "CoreViewer" capability in many Core Customization windows
- Graphically displays layout of RPM'd logic, and reports CLB/slice, LUT and
register utilization after the module is generated
- Supports Virtex, 4K, Spartan and Spartan-II architectures (Virtex-II cores
support to be added later)
- Activate by clicking on "Display Core Viewer after Generation" checkbox in
Core Customization window

8. Enhancements to HDL Flow
- get_models no longer needs to be run by the user.
o CORE Generator Verilog simulation models for cores shipped on the
3.1i CD are now provided in $XILINX/verilog/src/XilinxCoreLib
o CORE Generator VHDL simulation models for cores shipped on the
3.1i CD are now provided in $XILINX/vhdl/src/XilinxCoreLib
- Models for new IP updates will also be available already extracted, or
will be extracted during the installation process starting with the September
2000 release
- New vhdl_analyze_order file lists required compile order of the Coregen
VHDL models for simulation
- New verilog_analyze_order file lists CORE Generator Verilog
behavioral models in suggested compile order for compiled Verilog
- .VEO and .VHO templates are generated by default if a Verilog or
VHDL flow is selected in the Project Options dialog, respectively

9. New ASY symbol format support
- ASY file is always generated for each core by default to
- supports ECS integration
- supportsdynamic updating of core symbol pins in core
customization GUIs in response to user parameter selections
(newer Virtex cores only)

10. New coredb.xml file replaces resources.lib installed IP database file, and
new coredb utility can be used directly to update the new coredb.xml
installed cores database file

11. Improved Project Management
- Improved Project Chooser dialog
- New project locking feature prevents more than one user from writing to a
CORE Generator project at the same time

AR# 8194
Date 08/23/2002
Status Archive
Type General Article
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