General Description: The Virtex Variable Parallel Multiplier may show only 1 cycle of latency in Verilog behavioral simulation.
The problem has been tracked to a mismatch in the number and order of parameters passed from the Verilog .VEO instantiation template to the multiplier's Verilog behavioral model.
Solution
As a workaround, you can generate a post-NGDBUILD gate level simulation netlist using the Core's EDIF implementation netlist, as described in (Xilinx Solution #8065)
A fix will be available in the C_IP4 update scheduled for December 1999 release. Please check this web page for availability of this release: