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  3. AR# 8233: 2.1i COREGEN, C_IP2: Virtex Variable Parallel Multiplier model shows only a 1-cycle latency in Verilog behavioral simulation

AR# 8233

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2.1i COREGEN, C_IP2: Virtex Variable Parallel Multiplier model shows only a 1-cycle latency in Verilog behavioral simulation

Description

Keywords: multiplier, latency, virtex, verilog, behavioral, simulation

Urgency: standard

General Description:
The Virtex Variable Parallel Multiplier may show only 1 cycle of latency in Verilog behavioral
simulation.

The problem has been tracked to a mismatch in the number and order of parameters
passed from the Verilog .VEO instantiation template to the multiplier's Verilog behavioral model.

Solution

As a workaround, you can generate a post-NGDBUILD gate level simulation netlist
using the Core's EDIF implementation netlist, as described in (Xilinx Solution #8065)

A fix will be available in the C_IP4 update scheduled for December 1999 release.
Please check this web page for availability of this release:

http://www.xilinx.com/ipcenter/coregen/updates.htm#updatesCurrent
AR# 8233
Date 09/05/2001
Status Archive
Type General Article
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