How do I determine whether the DONE pin is being held Low externally or if the FPGA has not released the signal?
By default, the DONE pin is an open-drain driver that must be pulled up to achieve a logic High. This allows multiple FPGAs to be configured in a serial daisy chain.
When devices are configured in a serial daisy chain, upstream devices are fully programmed before they pass configuration data to downstream devices. After the upstream device is programmed, it releases its DONE pin and waits in the startup sequence until all other FPGAs release their DONE pins and the DONE signal goes High.
All Virtex and Virtex-II-based devices contain a programmable internal pull-up resistor on the DONE pad. This can be enabled with the "DriveDone" option in BitGen to cause the FPGA to actively drive the DONE signal High instead of simply releasing it. In a serial daisy chain, only the last device can utilize this option (otherwise, an upstream device will actively drive the DONE signal High once its configuration information is loaded, causing contention on the shared DONE signal).
How to determine whether a Virtex device has released its DONE pin
There is no direct way to verify that a Virtex device has released its DONE pin. For serial configuration modes, the DOUT pin can be monitored to determine whether the device has begun sending data downstream. Activity on the DOUT pin indicates that the device has finished loading its configuration data, that its CRC check has passed, and that the DONE pin has been released.
1. If a debug bitstream is being used, activity on the DOUT pin does not indicate that the FPGA has released its DONE pin.
2. This technique does not apply to SelectMAP configuration modes, as the DOUT pin becomes the BUSY signal for SelectMAP.
How to determine whether a Virtex-II device has released its DONE pin
With Virtex-II you can directly determine whether the DONE pin has been released by performing an Instruction Capture through JTAG. This register provides access to the internal "release_done" signal, which releases the DONE pin. For Virtex, the actual value of the DONE pin is reflected in each of these registers instead of the release_done signal, which means that this is not an option for Virtex.
Instruction Capture through JTAG
To perform an Instruction Capture through JTAG, reset the TAP, then move to the Shift-IR state. Clock TCK six times while holding TMS=0. The device will clock out the IR Capture value on its TDO pin. Bit 5 of the Instruction_Capture pattern indicates whether the DONE signal has been released. From the Virtex-II BSDL file:
attribute INSTRUCTION_CAPTURE of XC2V250_CS144 : entity is
-- Bit 5 is 1 when DONE is released (part of startup sequence)
-- Bit 4 is 1 if house-cleaning is complete
-- Bit 3 is ISC_Enabled
-- Bit 2 is ISC_Done
Double-check the STARTUP sequence options selected for bitstream generation. The "SyncToDone" option is recommended and is required if multiple FPGAs are daisy-chained in serial or express mode configuration. The SyncToDone option prevents the STARTUP sequence from continuing until the DONE pin is allowed to go High.
If the FPGA is daisy-chained, the DONE pin is probably being held Low by one of the other FPGAs. The recommended STARTUP options are:
For Virtex, Virtex-II, and their derivatives:
For 3000, 4000, and 5200-series devices: