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AR# 8258

2.1i : 9500 : Hitop : WARNING: CPLDFitter- The property SLOW set on the instance "<inst>" conflicts with the previous setting FAST.


Keywords : 9500, fast, slow, slew

Urgency : standard

General Description:

The 9500 devices have an option to set the slew rate to either fast or slow.
In the constraint file you can add the following constraint.

net <name> slow;

When an attempt to implement the design takes place, hitop ignores
the constraint with the following warning:

WARNING:CPLDFitter - The property SLOW set on the instance "<inst>"
conflicts with the previous setting FAST. Both settings are
ignored in favor of the fitter default.

This warning occurs when the design was synthesized from FPGA Express.
FPGA Express places FAST attribute on output signals which then confuses
the fitter software when it sees a SLOW constraint in the UCF.



One solution is to

1) Edit Synthesis constraints for FPGA Express
2) Click on the Ports tab
3) Set the slew for the nets in there.
4) The netlist will now have a slow attribute for that net.


Another resolution is to manually edit the netlist removing any attribute of 'fast'
on that net or replacing it with 'slow'.


The Xilinx Synthesis Tool (XST) included in the WebPack (http://www.xilinx.com/sxpresso/webpack.htm) does not have this
AR# 8258
Date Created 12/10/1999
Last Updated 06/13/2002
Status Archive
Type General Article