AR# 8262


4.1i 4KXLA MAP - "FATAL_ERROR: OldMap:x45maclb.c:204: - Unknown input pin Q."


Keywords: x45maclb, 204, unknown, input, pin, FPGA Express, XNF, latch, LDCE_1

Urgency: Standard

General Description:
My netlist can be mapped successfully into a 4KXL part, but MAP fails with the following error when I target a 4KXLA part:

FATAL_ERROR: OldMap:x45maclb.c:204: - Unknown input pin Q for CLB LATCH primitive. Process will terminate.


All the pin types in the LDCE_1 latches were incorrectly defined to be "B" instead of "I" or "O". LDCE_1 is not listed as a primitive in the FPGA Express library. Because of this, it is treated as a black box when it is instantiated. Verilog does not require pin directions to be defined for these types of instantiations, and since FPGA Express has no knowledge of this component, it will default to bidirectional. To solve this problem, simply define the LDCE_1 module as follows:

module LDCE_1 (G,CLR,GE,D,Q);
input G,CLR,GE,D;
output Q;

It will still be instantiated as a black box to be expanded by NGDBuild, but you will see that the pin directions are declared properly in the resulting XNF file.

The reason the design behaved differently in 4KXL than in 4KXLA is that the LDCE_1 is a primitive for the 4KXLA; however, for the 4KXL, a lower level LDCE is pulled in with valid pin types.
AR# 8262
Date 06/13/2002
Status Archive
Type General Article
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