AR# 8314


2.1i COREGEN, C_IP4: RAM-based SHIFT REGISTER behavioral model does not match backannotated simulation when CE = 'X'


Keywords: ram, based, shift, register, x, behavioral, ce, vhdl

Urgency: standard

General Description:
There is an inconsistency between the behavior of the Xilinx RAM-based Shift Register
behavioral model and the behavior of this module in a VHDL backannotated simulation when
the clock enable signal CE = 'X'.

When CE goes to 'X', the output of the Shift Register goes to 'X' after three clock cycles
in a backannotated simulation. In contrast, under the same conditions the output of the
behavioral model does not change.

Several cases of this have been observed in RAM-based Shift Register cores which were
fixed-length and which had a final output register.


To work around this problem in the behavioral model, please follow the procedure
described in (Xilinx Answer #8065) to generate a post-NGDBUILD model and use this
in place of the behavioral model supplied by the CORE Generator.
AR# 8314
Date 09/05/2001
Status Archive
Type General Article
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