AR# 8374

2.1i COREGEN, VERILOG: 'Error! Too many module instance parameter assignments [in] "XilinxCoreLib/async_fifo_v1_0.v", 839: C_GATE_BIT_V1_0'

Description

Keywords: Fifo, Coregen, IP, Asynchronous, fifo, Verliog, XL, Core

Urgency: Standard

General Description:
When compiling Coregen's Asychronous FIFO, the following error may be
seen:

"Too many module instance parameter assignments [Verilog-TMIPA]
"XilinxCoreLib/async_fifo_v1_0.v", 839:
C_GATE_BIT_V1_0 #(init_val, yes, yes, 1, no, yes
, no, no, no, yes, no, no, no, 2, "10", 1, "0"
, 0, 1) nand_fd(.I(nand_in), .O(fake_out), .clk(
clk), .q(q_out), .CE(vcc), .AINIT(rst), .ASET(
fake_in), .ACLR(f..."

Solution

1

The Asynchronous FIFO Verilog model contains several instantiations of the
C_GATE_BIT_V1_0 module.

The instance starting on line 839 in the FIFO model passes one extra parameter
value (19 total) instead of the 18 required to configure the C_GATE_BIT_V1_0.v
Verilog model. Two lines down from line 837 (the beginning of the declaration)
there is an extra "yes" entry which should be edited out of the model:

C_GATE_BIT_V1_0 #(init_val,
yes,
yes, <--------------------------- extra "yes" parameter entry
1,
no,
yes,
no,
no,
no,
yes,
no,
no,
no,
2,
"10", //c_nand,
1,
"0",
0,
1
)

2

This problem is fixed in the following tactical patch:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.tar.gz (UNIX), or
http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.zip (PC)

Extract the patch to your Xilinx directory.
AR# 8374
Date 08/24/2001
Status Archive
Type General Article