AR# 8388


2.1isp6 Solaris Install - Readme file for 2.1i Service Pack 6 for Solaris


Keywords: Service Pack, Readme, Solaris, software update, 2.1isp6, Service Pack 6

Urgency: Standard.

General Description:
This answer record contains information on the Readme file for 2.1i Service Pack 6 for Solaris.


This 2.1i Service Pack 6 Update is intended as an update to all 2.1i Alliance installations on Solaris workstations.

All fixes packaged in the previous 2.1i Service Packs are included in Service Pack 6. Installation of the earlier Service Packs is NOT necessary.

Implementation Update Installation Instructions:
1. Download the 21i_sp6_implementation_sol.tar.gz update file from
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 21i_sp6_implementation_sol.tar.gz
tar xvf 21i_sp6_implementation_sol.tar

3. Run "solalli.C22.5/setup".

Device Data Files Update Installation Instructions:
1. Download the 21i_sp6_data_sol.tar.gz update file from
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 21i_sp6_data_sol.tar.gz
tar xvf 21i_sp6_data_sol.tar

3. Run "soldata.C22.6/setup"

NOTE 1: The destination directory specified during the setup operation must contain an existing 2.1i installation. Only existing files will be updated. Any new device support not previously installed should first be installed from the 2.1i CD before the Service Pack update is added.

NOTE 2: The Xilinx 2.1i environment variable should be set before commencing installation of Service Pack 6.

For information on the contents of the Implementation Tools Update, please see (Xilinx Answer 8911).

The following products and issues are addressed in 2.1i Service Pack 6


2.1i NGDAnno - NGDAnno leaves Block RAM inputs unconnected if they are driven by more than one power/ground or constant signals.
(Xilinx Answer 6665)

2.1i Virtex NGDAnno - Virtex single- and dual-port RAM report setup violations for Physical simulation.
(Xilinx Answer 7322)

2.1i - Verilog UNISIM and Cadence Concept models are not using glbl.GSR for block RAM
(Xilinx Answer 7331)

2.1i Virtex NGDAnno - Back-annotated delay has added 3.7 ns to a 3-state signal on an IOB.
(Xilinx Answer 7336)

2.1i NGDAnno - "INTERNAL_ERROR:Anno:Ax.c:2094: - Ax::fixConfusedPins() cannot handle this configuration."
(Xilinx Answer 6913)


2.1i Virtex-E BitGen - The equations for the DLL feedback 2x memory cell in Virtex-E are incorrect.
(Xilinx Answer 8854)

2.1i Virtex BitGen - A Virtex bit file from BitGen with default options causes improper behavior on CLKDLL.
(Xilinx Answer 8244)

2.1i Virtex BitGen - "WARNING:Bitgen:73 - Can't find arc ...."
(Xilinx Answer 7186)


2.1i Constraints Editor - Spartan 20 PQ208 Prohibit I/O locations for configuration pins are incorrect.
(Xilinx Answer 7235)

2.1i Constraints Editor - Constraint_editor.exe: An application error has occurred. (Xilinx Answer 7050)


2.1i CORE Generator - Not all EDIF files are copied over when I generate cores made up of multiple EDIF files.
(Xilinx Answer 8497)

2.1i Foundation CORE Generator - "Line: 3 Wrong number of fields BUS" is reported on modules during symbol generation.
(Xilinx Answer 7151)

2.1i Foundation CORE Generator - "Unexpanded block error...because one or more pins on the block...were not found."
(Xilinx Answer 6853)

2.1i Foundation CORE Generator - Virtex Variable Parallel Multiplier optional pins appear in a Foundation symbol when they were not requested.
(Xilinx Answer 7397)


2.1i XC9500 Family Tsim - A TPTA2 timing value has been added.
(Xilinx Answer 8822)

2.1i XC9500 Family Hitop - Product terms are removed in the fitter when assigned to a different pin.
(Xilinx Answer 8502)

2.1i XC9500 Family Hitop - A Dr. Watson internal error occurs during timing optimization.
(Xilinx Answer 8824)

2.1i 9500/XL - A timing model incorrect for negative-edge triggered global clock signals.
(Xilinx Answer 7948)

2.1i 9500XL Hitop - Designs that fit in the 1.5i software do not fit in the 2.1i software.
(Xilinx Answer 8095)

2.1i 9500XL Hitop - Incorrect implementation of a <function> = VCC.
(Xilinx Answer 7314)

2.1i 9500/XL TAEngine - Program abnormally terminated.
(Xilinx Answer 8109)

2.1i Hitop - Hitop uses SLOW slew when routing an internal BUFG net through a GTS pin.
(Xilinx Answer 7760)

2.1i Hitop - Fitting Report shows VCCIO pins as TIE on an XC95288XL-BG256.
(Xilinx Answer 6683)

2.1i Hitop - Hitop is not fitting DFF -> INV -> OBUF correctly.
(Xilinx Answer 7337)


2.1i Design Manager - New behavior for UCF declaration has been introduced.
(Xilinx Answer 726)

2.1i Design Manager - When running pld_dsgnmgr through Mentor DM or using the "Design Manager" option from Exemplar's PAR tab, I cannot choose implementation options.
(Xilinx Answer 6554)

2.1i Design Manager - The server reports an exception error.
(Xilinx Answer 6660)


2.1i Floorplanner - Map file naming is causing problems for the Design Manager.
(Xilinx Answer 6438)


2.1i FPGA Editor - "Access violation (0xc0000005), Address 0x003652e0 (Edit CLB/IOB/Slice & Save)."
(Xilinx Answer 7713)

2.1i FPGA Editor - "ERROR:Portability:90 - Command line error: Switch '-usedpin' is unexpected."
(Xilinx Answer 7329)

2.1i FPGA Editor - Busy cursors are not used on many long processes.
(Xilinx Answer 7334)


2.1i Hardware Debugger - Parallel cable does not complete with Virtex chains.
(Xilinx Answer 7763)


2.1i JTAG Programmer - 9500/XL Deselecting Program Options -> "Erase before programming" does not work.
(Xilinx Answer 8538)

2.1i JTAG Programmer - XC1801 device support.
(Xilinx Answer 8851)

2.1i JTAG Programmer - Device support for the Spartan-II family.
(Xilinx Answer 8852)

2.1i JTAG Programmer - 1802 PROM support was added in the 2.1i software.
(Xilinx Answer 8264)

2.1i JTAG Programmer - Virtex-E BSDL files are available.
(Xilinx Answer 8312)

2.1i JTAG Programmer - "Error: JTAG - Unable to locate BSDL file 'c.bsd'."
(Xilinx Answer 8108)

2.1i 1800 JTAG Programmer - Is there JTAG support for the 1800-series PROMs?
(Xilinx Answer 6850)

2.1i Virtex JTAG Programmer - Virtex configuration requires an initial shutdown sequence.
(Xilinx Answer 7319)

2.1i JTAG Programmer - "Error:JTag- The boundary-scan 'program' operation is not supported..." reported when I use SVF for the 4002XL-PQpq100.
(Xilinx Answer 6764)

2.1i JTAG Programmer - The Done pin does not go High when I configure an 4010XL.
(Xilinx Answer 7049)


2.1i UNISIMS/SIMPRIMS - CLKDLL does not lock after RST is de-asserted.
(Xilinx Answer 1825)

2.1i XSI Library - Bidirectional I/O has an extra inversion inferred (IOBUF_N).
(Xilinx Answer 7470)

Synopsys FPGA Compiler 1998.08/1999.05 - Slew rate specifications on Virtex IOBs are ignored during synthesis.
(Xilinx Answer 6588)


2.1i XC4000XL MAP - "FATAL_ERROR:OldMap:x4emamerge.c:2410: - Illegal merge detected."
(Xilinx Answer 7142)

2.1i Virtex MAP - MAP does not put two unconstrained SRL16s into a single Virtex slice.
(Xilinx Answer 6793)

2.1i Virtex MAP - "FATAL_ERROR:xvkpu:xvkpulocal.c:246:1.3."
(Xilinx Answer 8092)

2.1i Virtex MAP - MAP uses the incorrect JF setting for a CLKDLLHF.
(Xilinx Answer 7709)

2.1i Virtex MAP - "Exception: Access Violation (oxc0000005), address:ox00255920."
(Xilinx Answer 7264)

2.1i Virtex MAP - A mapped design results in a sourceless net, leading to DRC errors.
(Xilinx Answer 7364)

2.1i Virtex MAP - The default input path delay element usage is being changed.
(Xilinx Answer 7728)

2.1i Virtex MAP - MAP hangs at "Reading NGD file ..." on an XCV1000 design.
(Xilinx Answer 7453)

2.1i Virtex MAP - The mapper creates an unroutable connection when F6MUX is driven by two F5MUXes.
(Xilinx Answer 7466)

2.1i Virtex MAP - "FATAL_ERROR:xvkpk:xvkpkslice.c:146:1.30"
(Xilinx Answer 7487)

2.1i Virtex MAP - MAP creates bad .pcf constraints from Floorplanner constraints.
(Xilinx Answer 7325)

2.1i 4000X* MAP - MAP writes a bad constraint, leading to "ERROR:OldMap:563 - Bel type "PAD" is not supported."
(Xilinx Answer 6319)

2.1i Virtex MAP - MAP trims an inverter when an FF pushed into the IOB.
(Xilinx Answer 7279)

2.1i Virtex MAP - Virtex mapper treats an OBUF driving PU, PD, or KEEPER inconsistently.
(Xilinx Answer 7349)

2.1i Virtex MAP - MAP configures a BUFT driven by PWR/GND in a way that will not work in the hardware.
(Xilinx Answer 7008)

2.1i Virtex MAP/PAR - Designs combining non-RLOC'd carry chains and macros fail.
(Xilinx Answer 7086)

2.1i Virtex MAP - "ERROR:xvkpu - Unable to obey design constraints..."
(Xilinx Answer 6708)

2.1i Virtex MAP - The Virtex packer is failing to process the local output directive properly.
(Xilinx Answer 7321)


2.1i Spartan-II NGDBuild - "ERROR:NgdHelpers:312 - logical block "$<>" of type "STARTUP_SPARTAN2 is unexpanded.
(Xilinx Answer 8424)

2.1i NGDBuild - NGDBuild is ignoring drive strength constraints attached to nets which drive IOB components (created from Constraints Editor)
(Xilinx Answer 7071)

2.1i NGDBuild - TNM_NET propagation through the DLL to no synchronous loads (two problems).
(Xilinx Answer 7351)


2.1i Spartan-II Package Files - The TQ144 Package has been added for Spartan-II.
(Xilinx Answer 8296)

2.1i Virtex-E Packages - The XV600E FG900 and XV1000E FG1156 packages contain incorrect banking information.
(Xilinx Answer 8298)

2.1i Spartan-II Package Files - New package files are available with Service Pack 3.
(Xilinx Answer 8118)

2.1i Package Files - An incorrect location for the Spartan40XL BG256 DONE pin is specified in the pad report.
(Xilinx Answer 7736)

2.1i SpartanXL - The CS280 packages are missing in the M2.1i software.
(Xilinx Answer 7326)

2.1i Package Files - The 40150XV BG432 package is incorrect.
(Xilinx Answer 7185)


2.1i Virtex PAR - "DesignRules:533 - Netcheck: Improper routing. Signal N141 is routed with too many unbuffered connections."
(Xilinx Answer 8925)

2.1i Spartan-XL PAR - The router gives poor results on XCS30XL and XCS40XL designs when compared to the 1.5i software.
(Xilinx Answer 8421)

2.1i Virtex PAR - MPPR and non MPPR runs give different results for the same cost table.
(Xilinx Answer 8371)

2.1i XV4000XL PAR - Guided PAR of XC4000XL device does not work in 2.1i Service Pack 1 or Service Pack 2.
(Xilinx Answer 7938)

2.1i Virtex MAP - An inversion between MUXCY and a flip-flop is dropped.
(Xilinx Answer 8490)

2.1i XV1000E PAR - A data file fix for XV1000E may improve placement results for some designs.
(Xilinx Answer 8297)

2.1i Virtex PAR - Router has difficulty connecting block RAM pins.
(Xilinx Answer 7813)

2.1i PAR - PAR and TRCE report different numbers for the same routing.
(Xilinx Answer 7827)

2.1i Virtex PAR - "FATAL_ERROR:Utilities:basagconjgradient.c:202: - CG SOLVER: residual."
(Xilinx Answer 8093)

2.1i Virtex-E PAR - The placer continues even if LVDS I/O comps have no locate constraints.
(Xilinx Answer 8094)

2.1i PAR - "Application error has occurred. Exception:Access Violation (0xc0000005), Address: 0x039313b9"
(Xilinx Answer 7245)

2.1i 4000XL/XV PAR - A PROHIBIT constraint is ignored.
(Xilinx Answer 7296)

2.1i Virtex PAR - A PC crash occurs after "Starting the placer".
(Xilinx Answer 7372)

2.1i 4000XL/XV PAR - A Dr. Watson error occurs during routing. "Access Violation (0xc0000005), Address: 0x0024b0b1."
(Xilinx Answer 7249)

2.1i Virtex PAR - The .par results file reports an incorrect number of logic levels.
(Xilinx Answer 7734)

2.1i Virtex PAR - The placer has been enhanced to use MAXSKEW preference to assign secondary global clock buffers for external clock nets.
(Xilinx Answer 7316)

2.1i Virtex PAR - "FATAL_ERROR:Place:xvkapanal.c:1860:"
(Xilinx Answer 6690)

2.1i Virtex PAR - A Virtex design takes too long to route PWR/GND signals.
(Xilinx Answer 6739)

2.1i SpartanXL PAR - PAR fails to produce consistent results when running a cost table twice.
(Xilinx Answer 7335)

2.1i Virtex PAR - Virtex designs with area constraints run out of memory during placement.
(Xilinx Answer 6953)

2.1i Virtex PAR - Router terminates and reports a segmentation fault during PWR/GND routing.
(Xilinx Answer 7064)

2.1i PAR - PAR does not clean up low-end results when running turns engine (ignores "-s")
(Xilinx Answer 7350)

2.1i Virtex PAR - The placer leaves the source pin of a high fanout net unplaced, leading to a router crash.
(Xilinx Answer 7345)

2.1i Virtex PAR - The placer ignores a list constraint involving IOB.
(Xilinx Answer 7078)

2.1i Spartan-XL PAR - "FATAL_ERROR:Route:basrtsanity.c:241: -Process will terminate."
(Xilinx Answer 7342)


2.1i Virtex Speed Files - A change has been made to correct optimistic Block RAM timing.
(Xilinx Answer 8910)

2.1i Spartan-II Speed Files - The Spartan-II speed grades are now marked ADVANCED.
(Xilinx Answer 8846)

2.1i Virtex Speed Files - The Virtex speed files have been modified to support the Power Estimator tool.
(Xilinx Answer 8845)

2.1i Virtex-E Speed Files - New speed files are available for Virtex-E.
(Xilinx Answer 8294)

2.1i Speed Files - Several speed file changes are available in Service Pack 3.
(Xilinx Answer 8117)

2.1i Virtex Speed Files - New Virtex Speed files are available in 2.1i Service Pack 1.
(Xilinx Answer 7327)

2.1i XC4000XV Speed Files - The 2.1i Service Pack 1 Update contains Preliminary XC4000XV speed data.
(Xilinx Answer 7330)

2.1i SpartanXL Speed Files - Updated speed files are available for -5 Preliminary speed grades.
(Xilinx Answer 7352)

2.1i Virtex Speed Files - Missing Virtex pin-to-pin timing values cause overly optimistic delays.
(Xilinx Answer 7341)


2.1i Timing Analyzer - A memory leak occurs when custom sources are selected.
(Xilinx Answer 8327)

2.1i Timing Analyzer - A bus error when Timing Analyzer is launched on an HP 10.20 platform.
(Xilinx Answer 7192)

2.1i 9500XL Timing Analyzer - Custom Report for CPLD causes a stack fault error (timingan.exe, mfc42.dll) or Process Exit Code 2.
(Xilinx Answer 7312)

2.1i Virtex Floorplanner - A crash occurs due to stack overflow.
(Xilinx Answer 7448)

2.1i Virtex Timing - Back-annotated Virtex timing under-reports delay.
(Xilinx Answer 6964)

2.1i 4000E/Spartan Timing - Back-annotated XC4000E and Spartan delays are under-reported.
(Xilinx Answer 6965)

2.1i Timing Analyzer - Timing Analyzer only produces a summary report of constraints with no paths for advanced analysis.
(Xilinx Answer 6825)

2.1i TRCE/NGDBUILD/Timing Analyzer/FPGA Editor - MIN delays and changing speed grades after implementation does not work
(Xilinx Answer 6959)

2.1i TRCE - Paths are reported against the wrong timing constraint.
(Xilinx Answer 7340)
AR# 8388
Date 10/10/2003
Status Archive
Type General Article
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