AR# 8388: 2.1isp6 Solaris Install - Readme file for 2.1i Service Pack 6 for Solaris
AR# 8388
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2.1isp6 Solaris Install - Readme file for 2.1i Service Pack 6 for Solaris
Description
Keywords: Service Pack, Readme, Solaris, software update, 2.1isp6, Service Pack 6
Urgency: Standard.
General Description: This answer record contains information on the Readme file for 2.1i Service Pack 6 for Solaris.
Solution
This 2.1i Service Pack 6 Update is intended as an update to all 2.1i Alliance installations on Solaris workstations.
All fixes packaged in the previous 2.1i Service Packs are included in Service Pack 6. Installation of the earlier Service Packs is NOT necessary.
Implementation Update Installation Instructions: 1. Download the 21i_sp6_implementation_sol.tar.gz update file from http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 2. Untar the downloaded file into an empty "staging" directory.
For example: cd /home/staging_dir gzip -d 21i_sp6_implementation_sol.tar.gz tar xvf 21i_sp6_implementation_sol.tar
3. Run "solalli.C22.5/setup".
Device Data Files Update Installation Instructions: 1. Download the 21i_sp6_data_sol.tar.gz update file from http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 2. Untar the downloaded file into an empty "staging" directory.
For example: cd /home/staging_dir gzip -d 21i_sp6_data_sol.tar.gz tar xvf 21i_sp6_data_sol.tar
3. Run "soldata.C22.6/setup"
NOTE 1: The destination directory specified during the setup operation must contain an existing 2.1i installation. Only existing files will be updated. Any new device support not previously installed should first be installed from the 2.1i CD before the Service Pack update is added.
NOTE 2: The Xilinx 2.1i environment variable should be set before commencing installation of Service Pack 6.
For information on the contents of the Implementation Tools Update, please see (Xilinx Answer 8911).
The following products and issues are addressed in 2.1i Service Pack 6
BACK ANNOTATION
2.1i NGDAnno - NGDAnno leaves Block RAM inputs unconnected if they are driven by more than one power/ground or constant signals. (Xilinx Answer 6665)
2.1i Virtex NGDAnno - Virtex single- and dual-port RAM report setup violations for Physical simulation. (Xilinx Answer 7322)
2.1i - Verilog UNISIM and Cadence Concept models are not using glbl.GSR for block RAM (Xilinx Answer 7331)
2.1i Virtex NGDAnno - Back-annotated delay has added 3.7 ns to a 3-state signal on an IOB. (Xilinx Answer 7336)
2.1i Constraints Editor - Spartan 20 PQ208 Prohibit I/O locations for configuration pins are incorrect. (Xilinx Answer 7235)
2.1i Constraints Editor - Constraint_editor.exe: An application error has occurred. (Xilinx Answer 7050)
CORE GENERATOR
2.1i CORE Generator - Not all EDIF files are copied over when I generate cores made up of multiple EDIF files. (Xilinx Answer 8497)
2.1i Foundation CORE Generator - "Line: 3 Wrong number of fields BUS" is reported on modules during symbol generation. (Xilinx Answer 7151)
2.1i Foundation CORE Generator - "Unexpanded block error...because one or more pins on the block...were not found." (Xilinx Answer 6853)
2.1i Foundation CORE Generator - Virtex Variable Parallel Multiplier optional pins appear in a Foundation symbol when they were not requested. (Xilinx Answer 7397)
CPLD
2.1i XC9500 Family Tsim - A TPTA2 timing value has been added. (Xilinx Answer 8822)
2.1i XC9500 Family Hitop - Product terms are removed in the fitter when assigned to a different pin. (Xilinx Answer 8502)
2.1i XC9500 Family Hitop - A Dr. Watson internal error occurs during timing optimization. (Xilinx Answer 8824)
2.1i 9500/XL - A timing model incorrect for negative-edge triggered global clock signals. (Xilinx Answer 7948)
2.1i 9500XL Hitop - Designs that fit in the 1.5i software do not fit in the 2.1i software. (Xilinx Answer 8095)
2.1i 9500XL Hitop - Incorrect implementation of a <function> = VCC. (Xilinx Answer 7314)
2.1i Hitop - Hitop uses SLOW slew when routing an internal BUFG net through a GTS pin. (Xilinx Answer 7760)
2.1i Hitop - Fitting Report shows VCCIO pins as TIE on an XC95288XL-BG256. (Xilinx Answer 6683)
2.1i Hitop - Hitop is not fitting DFF -> INV -> OBUF correctly. (Xilinx Answer 7337)
DESIGN MANAGER
2.1i Design Manager - New behavior for UCF declaration has been introduced. (Xilinx Answer 726)
2.1i Design Manager - When running pld_dsgnmgr through Mentor DM or using the "Design Manager" option from Exemplar's PAR tab, I cannot choose implementation options. (Xilinx Answer 6554)
2.1i Design Manager - The server reports an exception error. (Xilinx Answer 6660)
FLOORPLANNER
2.1i Floorplanner - Map file naming is causing problems for the Design Manager. (Xilinx Answer 6438)
2.1i JTAG Programmer - "Error:JTag- The boundary-scan 'program' operation is not supported..." reported when I use SVF for the 4002XL-PQpq100. (Xilinx Answer 6764)
2.1i JTAG Programmer - The Done pin does not go High when I configure an 4010XL. (Xilinx Answer 7049)
LIBRARY
2.1i UNISIMS/SIMPRIMS - CLKDLL does not lock after RST is de-asserted. (Xilinx Answer 1825)
2.1i XSI Library - Bidirectional I/O has an extra inversion inferred (IOBUF_N). (Xilinx Answer 7470)
Synopsys FPGA Compiler 1998.08/1999.05 - Slew rate specifications on Virtex IOBs are ignored during synthesis. (Xilinx Answer 6588)
2.1i Virtex PAR - A PC crash occurs after "Starting the placer". (Xilinx Answer 7372)
2.1i 4000XL/XV PAR - A Dr. Watson error occurs during routing. "Access Violation (0xc0000005), Address: 0x0024b0b1." (Xilinx Answer 7249)
2.1i Virtex PAR - The .par results file reports an incorrect number of logic levels. (Xilinx Answer 7734)
2.1i Virtex PAR - The placer has been enhanced to use MAXSKEW preference to assign secondary global clock buffers for external clock nets. (Xilinx Answer 7316)
2.1i Virtex PAR - "FATAL_ERROR:Place:xvkapanal.c:1860:1.1.2.21.2.1" (Xilinx Answer 6690)
2.1i Virtex PAR - A Virtex design takes too long to route PWR/GND signals. (Xilinx Answer 6739)
2.1i SpartanXL PAR - PAR fails to produce consistent results when running a cost table twice. (Xilinx Answer 7335)
2.1i Virtex PAR - Virtex designs with area constraints run out of memory during placement. (Xilinx Answer 6953)
2.1i Virtex PAR - Router terminates and reports a segmentation fault during PWR/GND routing. (Xilinx Answer 7064)
2.1i PAR - PAR does not clean up low-end results when running turns engine (ignores "-s") (Xilinx Answer 7350)
2.1i Virtex PAR - The placer leaves the source pin of a high fanout net unplaced, leading to a router crash. (Xilinx Answer 7345)
2.1i Virtex PAR - The placer ignores a list constraint involving IOB. (Xilinx Answer 7078)
2.1i Spartan-XL PAR - "FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 -Process will terminate." (Xilinx Answer 7342)
SPEED FILES
2.1i Virtex Speed Files - A change has been made to correct optimistic Block RAM timing. (Xilinx Answer 8910)
2.1i Spartan-II Speed Files - The Spartan-II speed grades are now marked ADVANCED. (Xilinx Answer 8846)
2.1i Virtex Speed Files - The Virtex speed files have been modified to support the Power Estimator tool. (Xilinx Answer 8845)
2.1i Virtex-E Speed Files - New speed files are available for Virtex-E. (Xilinx Answer 8294)
2.1i Speed Files - Several speed file changes are available in Service Pack 3. (Xilinx Answer 8117)
2.1i Virtex Speed Files - New Virtex Speed files are available in 2.1i Service Pack 1. (Xilinx Answer 7327)
2.1i XC4000XV Speed Files - The 2.1i Service Pack 1 Update contains Preliminary XC4000XV speed data. (Xilinx Answer 7330)
2.1i SpartanXL Speed Files - Updated speed files are available for -5 Preliminary speed grades. (Xilinx Answer 7352)