For example: cd /home/staging_dir gzip -d 21i_sp6_data_sol.tar.gz tar xvf 21i_sp6_data_sol.tar
3. Run "soldata.C22.6/setup"
NOTE 1: The destination directory specified during the setup operation must contain an existing 2.1i installation. Only existing files will be updated. Any new device support not previously installed should first be installed from the 2.1i CD before the Service Pack update is added.
NOTE 2: The Xilinx 2.1i environment variable should be set before commencing installation of Service Pack 6.
For information on the contents of the Implementation Tools Update, please see (Xilinx Answer 8911).
The following products and issues are addressed in 2.1i Service Pack 6
2.1i NGDAnno - NGDAnno leaves Block RAM inputs unconnected if they are driven by more than one power/ground or constant signals. (Xilinx Answer 6665)
2.1i Virtex NGDAnno - Virtex single- and dual-port RAM report setup violations for Physical simulation. (Xilinx Answer 7322)
2.1i - Verilog UNISIM and Cadence Concept models are not using glbl.GSR for block RAM (Xilinx Answer 7331)
2.1i Virtex NGDAnno - Back-annotated delay has added 3.7 ns to a 3-state signal on an IOB. (Xilinx Answer 7336)