AR# 8422

How do I instantiate the STARTUP block in VHDL/Verilog?

Description


General Description:

How do I instantiate the STARTUP block in VHDL/Verilog to use selected pins?



Note:

Most Synthesis tools provide an attribute to configure a design with GSR or GTS.

Use this example only if you need multiple pins in startup block.

Solution


VHDL Example

-- This example uses both GTS and GSR pins.

-- Unconnected STARTUP pins are omitted from component declaration.



library IEEE;

use IEEE.std_logic_1164.all;



entity setreset is

port (CLK: in std_logic;

DIN1 : in STD_LOGIC;

DIN2: in STD_LOGIC;

RESET: in STD_LOGIC;

GTSInput: in STD_LOGIC;

DOUT1: out STD_LOGIC;

DOUT2: out STD_LOGIC;

DOUT3: out STD_LOGIC);



end setreset ;



architecture RTL of setreset is

component STARTUP

port( GSR, GTS: in std_logic);

end component;



begin

startup_inst: STARTUP port map(GSR => RESET, GTS => GTSInput);

reset_process: process (CLK, RESET)

begin

if (RESET = '1') then

DOUT1 <= '0';

elsif ( CLK'event and CLK ='1') then

DOUT1 <= DIN1;

end if;

end process;



gtsprocess:process (GTSInput)

begin

if GTSInput = '0' then

DOUT3 <= '0';

DOUT2 <= DIN2;

else

DOUT2 <= 'Z';

DOUT3 <= 'Z';

end if;

end process;

end RTL;



Verilog Example

// This example uses both GTS and GSR pins

// Unused STARTUP pins are omitted from module declaration.



module setreset(CLK,DIN1, DIN2,RESET, GTSInput, DOUT1,DOUT2,DOUT3);

input CLK;

input DIN1;

input DIN2;

input RESET;

input GTSInput;

output DOUT1;

output DOUT2;

output DOUT3;



reg DOUT1;



STARTUP startup_inst(.GSR(RESET), .GTS(GTSInput));



always @(posedge CLK or posedge RESET)

begin

if (RESET)

DOUT1 = 1'b0;

else

DOUT1 = DIN1;



end



assign DOUT3 = (GTSInput == 1'b0)? 1'b0: 1'bZ;

assign DOUT2 = (GTSInput == 1'b0)? DIN2: 1'bZ;

endmodule



module STARTUP( GSR, GTS);

input GSR;

input GTS;

endmodule
AR# 8422
Date 12/13/2010
Status Archive
Type General Article