AR# 8477


12.1 Timing/Constraint - When I use a PERIOD constraint, the path from an SRL16 to a flip-flop is not analyzed


I placed a PERIOD timing constraint on the design, which is supposed to cover all paths between synchronous elements. Why are the paths from my SRL16 to flip-flops not covered during analysis?


The path described previously is an SRLUT-to-flip-flop, which is contained in a SLICE. Therefore, this is an internal clock-to-clock path within the SLICE, and this path is not currently analyzed.

This delay is fixed and can be located in the device data sheet under "Switching Characteristics".

AR# 8477
Date 12/15/2012
Status Active
Type General Article
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