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AR# 8520

Virtex-5/Spartan-3/E/A Configuration - In SelectMAP configuration mode, what is an ABORT? What causes it to occur?

Description

In SelectMAP configuration mode, what is an ABORT? What causes it to occur?

Solution

An ABORT is an interruption in the SelectMAP configuration or readback sequence that occurs when the state of WRITE_B changes while CS_B is asserted. During a configuration ABORT, the Virtex-II/Pro device drives a 32-bit status word on to the D[0:7] pins over the next four CCLK cycles. After the ABORT sequence finishes, you can re-synchronize the configuration logic and resume configuration.

ABORT Sequence Description

An ABORT is signaled during configuration as follows:

1. You perform a portion of the configuration that writes to registers. After 256 bits of download, at least one write operation has occurred.

2. You pull the /WRITE pin High while CS_B is still asserted (device is selected).

NOTE: When the SelectMAP WRITE signal is active (Low), the FPGA configuration data pins are inputs. When the SelectMAP WRITE signal is inactive (High), the FPGA configuration pins are outputs. If the CS_B signal is inactive (High), the configuration data pins are put into a 3-state condition.

3. BUSY goes High if CS_B remains asserted (Low). The FPGA drives the status word on to the Data pins if RDWR_B remains set for read control (logic High).

4. The ABORT ends when the /CS signal is de-asserted.

SelectMAP Configuration Abort Sequence
SelectMAP Configuration Abort Sequence

An ABORT is signaled during readback as follows:

1. You perform a portion of the readback that writes to registers.

2. You pull the /WRITE pin Low while CS_B is still asserted (device is selected).

NOTE: When the SelectMAP WRITE signal is active (Low), the FPGA configuration data pins are inputs. When the SelectMAP WRITE signal is inactive (High), the FPGA configuration pins are outputs. If the CS_B signal is inactive (High), the configuration data pins are put into a 3-state condition.

3. BUSY goes High if CS_B remains asserted (Low).

4. The ABORT ends when the /CS signal is de-asserted.

SelectMAP Readback Abort Sequence
SelectMAP Readback Abort Sequence

Note that ABORTs that occur during readback are not followed by a status word because the RDWR_B signal is set for write control (logic Low).

ABORT Status Words

During the configuration ABORT sequence, the device drives a status word on to the D[0:7] pins. The key for that status word is as follows:

D7: /cfgerr (a CRC error has occurred)

D6: dalign (interface logic has received a sync word)

D5: rip (a readback is in progress)

D4: /in_abort (an ABORT is in progress)

D3-D0: 1111

The ABORT sequence lasts for four CCLK cycles. During those cycles, the status word changes to reflect data alignment and ABORT status. A typical sequence is as follows:

11011111 => DALIGN = 1, IN_ABORT_B = 1

11001111 => DALIGN = 1, IN_ABORT_B = 0

10001111 => DALIGN = 0, IN_ABORT_B = 0

10011111 => DALIGN = 0, IN_ABORT_B = 1

After the last cycle, the synchronization word can be reloaded to establish data alignment.

Resuming Configuration

After an ABORT is completed (by de-asserting CS), the device must be re-synchronized. After re-synchronizing, you can resume configuration by sending the last configuration packet that was in progress when the ABORT occurred. Alternately, you can restart the configuration from the beginning.

For further information on ABORTs and Virtex configuration, please refer to the Xilinx Application Note (Xilinx XAPP138): "Virtex FPGA Series Configuration and Readback", or to the Virtex and Virtex-II Data Sheets, available at:

http://www.xilinx.com/support/documentation/index.htm

AR# 8520
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article