AR# 8525


2.1i SP5 - 2.1i Service Pack 5 update


Keywords: Service, Pack, 2.1i, update,

Urgency: Standard

General Description:

Contained within this Answer is complete list of all changes included in the M2,1i Service Pack 5 Update..


The Service Pack Update Page is located at:

The following issues are addressed by the 2.1i Service Pack 5 Update:


(Xilinx Answer #6847) : 2.1i NGDBuild - msvcrt.dll conflict; ucf file size limitations on
Windows NT/95.

(Xilinx Answer #7016) : 2.1i NGDBuild - Causes Dr Watson on Windows NT 4.0 SP3 at
Address: 0x780125b3.

(Xilinx Answer #7071) : 2.1i NGDBuild - NGDBuild ignoring drive strength constraints
attached to nets which drive IOB components (created from constraints editor)

(Xilinx Answer #7351) : 2.1i NGDBuild - TNM_NET propagation thru DLL to no
synchronous loads (two problems).


(Xilinx Answer #7142): 2.1i XC4000XL Map -
FATAL_ERROR:OldMap:x4emamerge.c:2410: - Illegal merge detected

(Xilinx Answer #6793): 2.1i Virtex MAP - Map will not put two unconstrained SRL16s
into a single Virtex slice.

(Xilinx Answer #8490): 2.1i Virtex Map - Inversion between MUXCY and Flop is

(Xilinx Answer #8092) : 2.1i Virtex Map - FATAL_ERROR:xvkpu:xvkpulocal.c:246:1.3.

(Xilinx Answer #7709) : 2.1i Virtex Map - Map uses the incorrect JF setting for a

(Xilinx Answer #7325) : 2.1i Virtex Map - Map creates bad .pcf constraints from floorplanner

(Xilinx Answer #7264) : 2.1i Virtex Map - exception: Access Violation (oxc0000005),

(Xilinx Answer #7364) : 2.1i Virtex Map - Mapped design results in sourceless net leading to
DRC errors.

(Xilinx Answer #7728) : 2.1i Virtex Map - The default input path delay element usage is being

(Xilinx Answer #7453) : 2.1i Virtex Map - Map hangs at "Reading NGD file ..." on XCV1000

(Xilinx Answer #7466) : 2.1i Virtex Map - Mapper creates unroutable connection when F6mux
is driven by two F5muxes.

(Xilinx Answer #7487) : 2.1i Virtex Map - FATAL_ERROR:xvkpk:xvkpkslice.c:146:1.30

(Xilinx Answer #7325) : 2.1i Virtex Map - Map creates bad .pcf constraints from floorplanner

(Xilinx Answer #6319) : 2.1i 4000X* Map - Map writes bad constraint leading to error:
ERROR:OldMap:563 - Bel type "PAD" is not supported.

(Xilinx Answer #7279) : 2.1i Virtex Map - Map trims inverter when FF pushed into IOB.

(Xilinx Answer #7349) : 2.1i Virtex Map - Virtex mapper treats OBUF driving PU, PD, or
KEEPER inconsistently.

(Xilinx Answer #7008) : 2.1i Virtex Map - Map may configure a BUFT driven by PWR/GND
in a way that will not work in the hardware.

(Xilinx Answer #7086) : 2.1i Virtex Map/PAR - Designs combining non-RLOC'd carry chains
and macros may fail.

(Xilinx Answer #6708) : 2.1i Virtex Map - ERROR:xvkpu - Unable to obey design

(Xilinx Answer #7321) : 2.1i Virtex Map - The Virtex packer is failing to process the local
output directive properly.


(Xilinx Answer #7938): 2.1i XV4000XL PAR - Guided PAR of XC4000XL device does not
work in 2.1i Service Pack 1 or Service Pack 2.

(Xilinx Answer #8297) : 2.1i XV1000E PAR - A data file fix for XV1000E may improve
placement results for some designs.

(Xilinx Answer #7813) : 2.1i Virtex PAR - Router has difficulty connecting Block RAM pins.

(Xilinx Answer #7827) : 2.1i PAR - PAR and TRCE report different numbers for the same

(Xilinx Answer #8093) : 2.1i Virtex PAR -
FATAL_ERROR:Utilities:basagconjgradient.c:202: - CG SOLVER: residual.

(Xilinx Answer #8094) : 2.1i Virtex-E PAR - Placer continues even if LVDS IO comps have
no locate constraints.

(Xilinx Answer #7245) : 2.1i PAR - Application error has occurred. Exception:Access Violation
(0xc0000005), Address: 0x039313b9

(Xilinx Answer #7296) : 2.1i 4000XL/XV PAR - Prohibit constraint ignored.

(Xilinx Answer #7372) : 2.1i Virtex PAR - PC only crash occurs after "Starting the placer".

(Xilinx Answer #7249) : 2.1i 4000XL/XV PAR - Dr Watson during routing. Access Violation
(0xc0000005), Address: 0x0024b0b1.

(Xilinx Answer #7734) : 2.1i Virtex PAR - The .par results file reports incorrect number of
logic levels

(Xilinx Answer #7316) : 2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW
preference to assign secondary global clock buffers for external clock nets.

(Xilinx Answer #6690) : 2.1i Virtex PAR -

(Xilinx Answer #6739) : 2.1i Virtex PAR - Virtex design is taking too long to route PWR/GND

(Xilinx Answer #7335) : 2.1i SpartanXL PAR - PAR fails to produce consistent results when
running a cost table twice.

(Xilinx Answer #6953) : 2.1i Virtex PAR - Virtex designs with area constraints may run out of
memory during placement.

(Xilinx Answer #7064) : 2.1i Virtex PAR - Router terminates with Segmentation fault during
PWR/GND routing.

(Xilinx Answer #7350) : 2.1i PAR - PAR does not cleanup low-end results when running turns
engine (ignores -s)

(Xilinx Answer #7345) : 2.1i Virtex PAR - Placer leaves source pin of high fanout net
unplaced, leading to router crash.

(Xilinx Answer #7078) : 2.1i Virtex PAR - Placer ignores list constraint involving IOB.

(Xilinx Answer #7342) : 2.1i SpartanXL PAR -
FATAL_ERROR:Route:basrtsanity.c:241: -Process will terminate.


(Xilinx Answer #8327): 2.1i Timing Analyzer - Memory leak occurs when selecting
custom sources.

(Xilinx Answer #7948): 2.1i 9500/XL - Timing model incorrect for negative edge
triggered global clock signals

(Xilinx Answer #7192) : 2.1i Timing Analyzer - Bus error when launched on the HP 10.20

(Xilinx Answer #7312) : 2.1i 9500XL Timing Analyzer - Custom Report for CPLD gives stack
fault error (timingan.exe, mfc42.dll) or Process Exit Code 2.

(Xilinx Answer #7448) : 2.1i Virtex Floorplanner - Crashes due to stack overflow.

(Xilinx Answer #6964) : 2.1i Virtex Timing - There are two known where back annotated
Virtex timing under reports delay.

(Xilinx Answer #6965) : 2.1i 4KE/Spartan Timing - There is a known case where back
annotated xc4000e and Spartan delays are under reported.

(Xilinx Answer #6825) : 2.1i Timing Analyzer - Timing Analyzer only produces a summary
report of constraints with no paths for advanced analysis.

(Xilinx Answer #6959) : 2.1i TRCE/NGDBUILD/Timing Analyzer/FPGA Editor - MIN delays
& changing speed grades after implementation does not work

(Xilinx Answer #7340) : 2.1i TRCE - Paths are reported against the wrong timing constraint.

(Xilinx Answer #7341) : 2.1i Virtex Speed Files - Missing Virtex pin-to-pin timing values cause
overly optimistic delays


(Xilinx Answer #7322) : 2.1i Virtex Ngdanno - Virtex single and dual port RAM give setup
violations for Physical Sim only.

(Xilinx Answer #7331) : 2.1i - Verilog UNISIM and Cadence Concept models are not using
glbl.GSR for Block RAM

(Xilinx Answer #7336) : 2.1i Virtex Ngdanno - Back annotated delay has 3.7ns added to
tristate signal on an IOB.

(Xilinx Answer #6913) : 2.1i Ngdanno - INTERNAL_ERROR:Anno:Ax.c:2094: -
Ax::fixConfusedPins() cannot handle this configuration.


(Xilinx Answer #7763) : 2.1i Hardware Debugger - Parallel cable doesn't complete with Virtex


(Xilinx Answer #8244) : 2.1i Virtex Bitgen - Virtex bit file from bitgen with default
options causes improper behavior on CLKDLL.

(Xilinx Answer #7186) : 2.1i Virtex Bitgen - "WARNING:Bitgen:73 - Can't find arc ...."


(Xilinx Answer #726) : 2.1i Design Manager: New behavior for UCF declaration introduced.

(Xilinx Answer #6554) : 2.1i Design Manager - Running pld_dsgnmgr through Mentor DM or
using the Design Manager option from Exemplar's P&R tab, can not choose options for

(Xilinx Answer #7328) : 2.1i Design Manager - DM Overwrite Last Version does not work on
win95/98 & WS

(Xilinx Answer #6660) : 2.1i Design Manager - The server threw an exception

(Xilinx Answer #7343) : 2.1i General - Help -> About Project Manager does not display
Service Pack revision information.


(Xilinx Answer #8264): 2.1i JTAG Programmer - 1802 PROM support added in 2.1i SP5.

(Xilinx Answer #8312) : 2.1i JTAG Programmer - Virtex-E BSDL files are available.

(Xilinx Answer #8108) : 2.1i JTAG Programmer - Error: JTAG - Unable to locate BSDL file

(Xilinx Answer #6850) : 2.1i 1800 JTAG Programmer - Is there JTAG support for the 1800
series PROMs?

(Xilinx Answer #7319) : 2.1i Virtex JTAG Programmer - Virtex configuration requires
shutdown sequence at beginning

(Xilinx Answer #6764) : 2.1i JTAG Programmer - Error:JTag- The boundary-scan 'program'
operation is not supported ... using SVF for the 4002xl-pq100

(Xilinx Answer #7049) : 2.1i JTAG Programmer - Done does not go high when configuring


(Xilinx Answer #8095) : 2.1i 9500XL Hitop - Designs that fit in 1.5i do not fit in 2.1i.

(Xilinx Answer #7314) : 2.1i 9500XL Hitop - Incorrect implementation of a <function> =

(Xilinx Answer #8109) : 2.1i 9500/XL TAEngine - Program abnormally terminated.

(Xilinx Answer #7760) : 2.1i Hitop - Hitop uses SLOW slew when routing internal BUFG net
through GTS pin.

(Xilinx Answer #6683) : 2.1i Hitop - Fitting Report shows VCCIO pins as TIE on

(Xilinx Answer #7337) : 2.1i Hitop - Hitop not fitting DFF--> INV --> OBUF correctly.


(Xilinx Answer #6438) : 2.1i Floorplanner - Map file naming is causing problems for the
Design Manager.


(Xilinx Answer #7713): 2.1i FPGA Editor - Access violation (0xc0000005), Address
0x003652e0 (Edit CLB/IOB/Slice & Save)

(Xilinx Answer #7329) : 2.1i FPGA Editor - ERROR:Portability:90 - Command line error:
Switch '-usedpin' is unexpected.

(Xilinx Answer #7334) : 2.1i FPGA Editor - Busy cursors are not used on many long


(Xilinx Answer #8497): 2.1i COREGEN - Not all EDIF files may be copied over when
generating cores made up of multiple EDIF files.

(Xilinx Answer #7151) : 2.1i Foundation COREGEN - "Line: 3 Wrong number of fields BUS"
on modules during symbol generation.

(Xilinx Answer #6853) : 2.1i Foundation COREGEN - Unexpanded block error ... because one
or more pins on the block ... were not found.

(Xilinx Answer #7397) : 2.1i Foundation COREGEN - Virtex Variable Parallel Multiplier
optional pins appear in a Foundation symbol even when not requested.

(Xilinx Answer #6890) : 2.1i Foundation COREGEN - Coregen may not be able to locate the
Foundation install directory on Windows.


(Xilinx Answer #8294): 2.1i Virtex-E Speed Files - New speed files are available
for Virtex-E.

(Xilinx Answer #8117) : 2.1i Speed Files - There are several speed file changes available in
Service Pack 3.

(Xilinx Answer #7327) : 2.1i Virtex Speed Files - New Virtex Speed files are available in 2.1i
Service Pack 1.

(Xilinx Answer #7330) : 2.1i XC4000XV Speed Files - The 2.1i Service Pack 1 Update
contains Preliminary XC4000XV speed data.

(Xilinx Answer #7352) : 2.1i SpartanXL Speed Files - Updated speed files are available for -5
Preliminary speed grades.


(Xilinx Answer #8296) : 2.1i Spartan2 Package Files - The TQ144 Package has been
added for Spartan2.

(Xilinx Answer #8298) :2.1i Virtex-E Packages - The XV600E FG900 and XV1000E
FG1156 packages have bad banking information.

(Xilinx Answer #8118) : 2.1i Spartan2 Package Files - New package files are available with
Service Pack 4.

(Xilinx Answer #7736) : 2.1i Package Files - Incorrect location for Spartan40XL BG256
DONE pin specified in the pad report.

(Xilinx Answer #7326) : 2.1i SpartanXL - The CS280 packages are missing in M2.1i

(Xilinx Answer #7185) : 2.1i Package Files - The 40150xv BG432 package is incorrect.


(Xilinx Answer #1825) : 2.1i UNISIMS/SIMPRIMS - CLKDLL doesn't lock after RST is

(Xilinx Answer #7470) : 2.1i XSI Library - Bidirectional I/O has extra inversion inferred

(Xilinx Answer #6588): Synopsys FPGA Compiler 1998.08/1999.05 - Slew rate specifications
on Virtex IOBs are ignored during synthesis.


(Xilinx Answer #7235) : 2.1i Constraints Editor - Spartan 20 PQ208 Prohibit IO locations for
configuration pins are incorrect.

(Xilinx Answer #7050) : 2.1i Constraints Editor - Constraint_editor.exe: An application error
has occurred.

AR# 8525
Date 04/28/2000
Status Archive
Type General Article
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