General Description: When a bidirectional signal is placed inside a macro (not on the top level) in a design, the Foundation simulator may not simulate the signal correctly in timing simulation. It may appear in the simulator that the signal is an output rather than a bidirectional signal.
This is due to the way the back-annotation program interprets bidirectional signals that are not on the top level of the design hierarchy.
A possible way to work-around the problem is to disable the "Correlate Netlist to Input Design" option in the Timing Simulation stage of implementation. To disable this option:
1. From the Project Manager, select Implementation -> Options 2. Click the Edit Options button next to Simulation 3. On the General tab, ensure that "Correlate Netlist to Input Design" is not selected
It is recommended that all ports of a design be placed on the top level of the design hierarchy. This practice will ensure that the design will correctly simulate in the Foundation simulator.