General Description: During the synthesis of a file, a number of warnings similar to the following are displayed:
"Warning: Cannot link to cell 'cell_name' to its reference design 'component_name'. (FPGA-LINK-2)"
where "component_name" is an instatiated component.
This warning is normal for all instantiated components in your code. If the component is a primitive, no action is needed.
NOTE: For 3000, 4000e, 5200 and 9500: If the component is a macro, you must copy the .xnf netlist from the Fndtn\Synth\xilinx\macros\<device family> to your project directory. To find components that are macros, check the Libraries Guide.