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AR# 8552

Modelsim (MTI) VHDL Coregen: Using a Generate Statment I can not get my simulation to run (Configuration)

Description

Keywords: configuration, generate, macro, multiple instances, functional simulation

Urgency: Standard

General Description:

I am using a VHDL generate statement to create multiple instances of
the same macro, and using a configuration statement to bind the compiled
behavioral model to this component name. When I simulate the design
I am getting all 'X' out of the Coregen macro, and it never changes.

Solution

Using the generate statement adds another level of "hierarchy" when it
comes to defining the configuration statement. To properly get the
compiled behavioral model bound to a component (all the same component),
a "for all" statement can be used in the following manner (top.vhd top_cfg.vhd):

Note: This example does not have a testbench.

-------------------------------------------------
-- Top Level VHDL file top.vhd
-------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity top is
port (
in1: in STD_LOGIC_VECTOR (1 DOWNTO 0);
S: in STD_LOGIC_vector (0 downto 0);
outp: out STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end top;

architecture top_arch of top is

component mymux
port (M: IN std_logic_VECTOR(1 downto 0);
S: IN std_logic_VECTOR(0 downto 0);
O: OUT std_logic);
end component;

begin

mygenerate: for i in 0 to 7 generate
multiple_mux: mymux
port map (M => in1, S => S, O => outp(i));
end generate;

end top_arch;

CONFIGURATION cfg_top OF top IS
FOR top_arch
end for;
end cfg_top;

--------------------------------------------------
-- Configuration file top_cfg.vhd
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library xilinxcorelib;

CONFIGURATION cfg_top OF top IS
FOR top_arch
for mygenerate
for all : mymux use entity
XilinxCoreLib.C_MUX_BIT_V1_0(behavioral)
generic map(c_sinit_val => "0",
c_sync_enable => 0,
c_has_ainit => 0,
c_sync_priority => 1,
c_has_sinit => 0,
c_ainit_val => "0",
c_inputs => 2,
c_has_sset => 0,
c_sel_width => 1,
c_has_q => 0,
c_has_o => 1,
c_has_aset => 0,
c_has_sclr => 0,
c_has_ce => 0,
c_has_aclr => 0,
c_enable_rlocs => 1);
end for;
end for;
end for;
end cfg_top;
AR# 8552
Date Created 08/31/2007
Last Updated 10/01/2008
Status Archive
Type General Article