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  3. AR# 8647: 2.1i COREGEN, C_IP4: Asynchronous FIFO model does not appear to increment WR_COUNT properly in Verilog-XL simulation

AR# 8647

2.1i COREGEN, C_IP4: Asynchronous FIFO model does not appear to increment WR_COUNT properly in Verilog-XL simulation

Description

Keywords: asynchronous fifo, wr_count

Urgency: hot

General Description:

The Asynchronous FIFO WR_COUNT output does not appear to increment properly
in Verilog-XL behavioral simulation. It has been observed typically at the start of a simulation,
but is not limited to this.

The problem appears to be specific to the Verilog-XL simulator, as it does not reproduce in
SILOS or ModelSIM simulators.











Solution

This problem is fixed in the following tactical patch:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.tar.gz (UNIX), or
http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.zip (PC)

Extract the patch to your Xilinx directory.
AR# 8647
Date 09/05/2001
Status Archive
Type General Article