General Description: In some cases, Synplify does not infer clock-enable or reset properly. For example, the following construct might get synthesized to FDR/FDE instead of FDRE:
always@ (posedge clk) if (reset) q <= "1010" else if (enable) q <= d;
This is a known issue. Synplify is looking into recognizing more enable or reset signals in the 6.2 release, but a few special cases may still trigger this problem.
Synplicity has filed bug #14321.
Solution
1
A work-around is to set the following attribute on the enable signal:
attribute syn_keep: boolean; attribute syn_direct_enable: boolean; attribute syn_keep of enable: signal is true; attribute syn_direct_enable of enable: signal is true;
SDC
define_attribute {n:enable} syn_direct_enable {1}
NOTE: "Enable" is the clock-enable net.
2
This solution might not work for Spartan devices. A bug has been filed and is scheduled to be fixed in the Synplify 6.1 release, which is scheduled for release in August/September, 2001.
In the meantime, consider these work-arounds:
1. Instantiate the FDCE manually to access the CE pin. 2. Generate a LogiBLOX counter and instantiate it in the HDL file.
NOTE: The COREGen counter is not available for Spartan devices.
3
If the "syn_direct_enable" attribute does not solve the problem, examine the enable signals and ensure that you are not assigning logic during signal declaration.