We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8750

Virtex - Why does the input setup time for I/O FFs increase as the device size increases?


The IOB input switching characteristics on the Virtex data sheet indicates that the setup time of I/O FFs increases as the device size increases. Why does the setup time increase with respect to the device size?


In Virtex parts, the input delay is designed to be greater than the global clock delay so that when the input delay is used, one will have zero hold time with respect to the global clock. The global clock delay increases with part size, so we designed the input delay to increase accordingly.

The Virtex data sheet also has the pin-to-pin setup time numbers (with and without DLL), these numbers do not increase as much as the device size. This is because the larger clock delay for the larger parts helps cancel some of the increase out.

AR# 8750
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked