What are the I/O switching levels during EXTEST (boundary scan interconnect testing)?
For unconfigured devices, I/Os will drive rail-rail between Ground and the voltage level on the VCCO pin in that bank. If the VCCO pin for that bank is at 3.3V, the I/O will drive at LVTTL levels, a 12mA drive strength, and a slow slew rate.
When sensing voltage levels applied to the pin during EXTEST or SAMPLE/PRELOAD, Vih=2.0V.
For configured devices, IOBs will retain their user configuration during boundary scan testing. For example, if an IOB is configured for GTL+, the IOB will drive and sense at GTL+ levels.
Related Answer Records:
- For information on the switching levels of the JTAG input pins, please see (Xilinx Answer 7738) For information on the TDO output voltage levels, please see (Xilinx Answer 8522) For more information on boundary scan tests for configured Xilinx devices, please see (Xilinx Answer 6664) For information on IBIS simulations for JTAG pins, please see (Xilinx Answer 12085)