AR# 8778: 3.1i COREGen, Leapfrog - CORE Generator VHDL models use non-IEEE standard std_logic_unsigned & std_logic_arith libraries
3.1i COREGen, Leapfrog - CORE Generator VHDL models use non-IEEE standard std_logic_unsigned & std_logic_arith libraries
Keywords: 1164, summit, leapfrog, vhdl, NC VHDL,
General Description: The CORE Generator VHDL models use non-IEEE standard std_logic_arith package and std_logic_unsigned libraries. These packages are not part of the IEEE 1164 standard. They are actually a Synopsys library that is supported by MTI, but not by Cadence Leapfrog.
This prevents users of the Cadence Leapfrog and Summit simulators from performing behavioral simulation of COREGen modules, since these simulators comply with the IEEE 1164 standard and do not ship these libraries. There may also be other simulators by Cadence which may not support these libraries, either.
There is no workaround for this issue at this time other than going into post-NGDBuild, post-MAP or post-PAR simulation.