What is the maximum JTAG clock (TCK) frequency for Xilinx devices?
The maximum configuration clock rate varies depending on the device family, as follows:
XC4000 - 5 Mhz
XC9500 - 10 Mhz
Virtex - 33 Mhz
For more information, refer to the appropriate BSDL file.
attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);
This indicates that the maximum frequency is 10 Mhz.
attribute TAP_SCAN_CLOCK of TCK : signal is (33.0e6, BOTH);
This indicates that the maximum frequency is 33 Mhz.
For information on the maximum TCK speed for Xilinx configuration cables, please refer to (Xilinx Solution 9803).